- Implement schematic netlist parser with S-expression parsing
- Create netlist tools for extraction and connection analysis
- Add resources for netlist and component connection reporting
- Include documentation with usage guide and troubleshooting
- Register new tools and resources in server configuration
This enables extracting component connections from KiCad schematics
and analyzing connectivity between components.
Implements a more reliable PCB thumbnail generation feature using two methods:
- Primary: pcbnew Python module for high-quality rendering
- Fallback: pcbnew_cli for environments without Python modules
Adds detailed progress reporting and comprehensive error handling.
Includes documentation in docs/thumbnail_guide.md.
This commit implements comprehensive DRC support including:
- DRC check tool integration with both pcbnew Python module and CLI fallback
- Detailed DRC reports as resources with violation categorization
- Historical tracking of DRC results with visual trend analysis
- Comparison between current and previous DRC runs
- New prompt templates for fixing violations and custom design rules
- Full documentation in drc_guide.md
The DRC system helps users track their progress over time, focusing on the
most critical design rule violations as they improve their PCB designs.
