KiCad 9 nests violations under sheets[].violations instead of
a top-level violations key. The parser now iterates all sheets
and aggregates violations, with a fallback for flat format.
no_connects now accept {pin_ref, pin_number} as an alternative to
{x, y} coordinates, matching the pattern used by labels. Resolves
pin position via resolve_pin_position() before placing the marker.
snap_to_grid() used 2.54mm default grid for symbol position,
silently rounding sub-2.54mm stub lengths up and causing shorts
on tightly-spaced connectors. Now uses 1.27mm fine grid.
add_hierarchical_sheet now returns sheet_uuid and parent_uuid.
apply_batch accepts these as optional params to call
set_hierarchy_context() before placing components, fixing
kicad-cli netlist export for hierarchical designs.
330 power symbols placed across 10 sheets but zero power nets appear in
kicad-cli export. Affects both mckicad and generate_schematic.py output.
Instance path mismatch identified as secondary issue. Workaround: use
verify_connectivity which reads power symbols via kicad-sch-api natively.
Label collision detection: resolve_label_collision() shifts different-net
labels that share the same (x,y) coordinate by 1.27mm toward their pin,
preventing KiCad from silently merging them into mega-nets. Integrated
at both label placement points in apply_batch.
Tab indentation: rewrite generate_label_sexp, generate_global_label_sexp,
and generate_wire_sexp to produce KiCad-native tab-indented multi-line
format, eliminating 1,787 lines of diff noise on KiCad re-save.
Intersheetrefs property now uses (at 0 0 0) placeholder.
Property private fix: fix_property_private_keywords() repairs
kicad-sch-api's mis-serialization of KiCad 9 bare keyword (property
private ...) as quoted (property "private" ...), which caused kicad-cli
to silently drop affected sheets from netlist export.
243 tests pass, ruff + mypy clean.
Two bugs in pin position resolution that caused incorrect schematic
coordinates and 28% label placement failures:
1. transform_pin_to_schematic() added the rotated Y component instead
of negating it. lib_symbol pins use Y-up; schematics use Y-down.
Fix: comp_y + ry -> comp_y - ry.
2. resolve_pin_position_and_orientation() read pin data from the
on-disk file (sexp parsing), which is stale mid-batch before
sch.save(). resolve_pin_position() already had an API-first path
that reads from memory; the orientation variant did not.
Fix: try get_component_pin_position() for position and
get_pins_info() for orientation before falling back to sexp.
Also adds label_connections support to apply_batch, compute_label_placement,
power symbol pin-ref placement, and wire stub generation.
This commit introduces a new circuit pattern recognition system that can
automatically identify common circuit patterns in KiCad schematics, including:
- Power supply circuits (linear regulators, switching converters)
- Amplifier circuits (op-amps, transistor amplifiers)
- Filter circuits (passive and active)
- Oscillator circuits (crystal, RC, IC-based)
- Digital interfaces (I2C, SPI, UART, USB)
- Microcontroller circuits
- Sensor interfaces
The implementation includes:
- Pattern recognition algorithms for common components
- Component value extraction and normalization utilities
- MCP tools for running pattern analysis
- MCP resources for displaying formatted results
- Comprehensive documentation
Users can easily extend the pattern recognition by adding new component
patterns or circuit recognition functions.
- Implement schematic netlist parser with S-expression parsing
- Create netlist tools for extraction and connection analysis
- Add resources for netlist and component connection reporting
- Include documentation with usage guide and troubleshooting
- Register new tools and resources in server configuration
This enables extracting component connections from KiCad schematics
and analyzing connectivity between components.
Implements a more reliable PCB thumbnail generation feature using two methods:
- Primary: pcbnew Python module for high-quality rendering
- Fallback: pcbnew_cli for environments without Python modules
Adds detailed progress reporting and comprehensive error handling.
Includes documentation in docs/thumbnail_guide.md.
This commit implements comprehensive DRC support including:
- DRC check tool integration with both pcbnew Python module and CLI fallback
- Detailed DRC reports as resources with violation categorization
- Historical tracking of DRC results with visual trend analysis
- Comparison between current and previous DRC runs
- New prompt templates for fixing violations and custom design rules
- Full documentation in drc_guide.md
The DRC system helps users track their progress over time, focusing on the
most critical design rule violations as they improve their PCB designs.
