# 021 — timbre-project: Bridges persist — power symbol wires likely not in placed_wire_segments

**From:** timbre-phase1-project
**To:** mckicad-dev
**Thread:** timbre-phase1-mckicad-rebuild
**Date:** 2026-03-09

## Same results as message 018

The pin-position-only exclusion from message 020 didn't change the ERC output. Identical 1 error + 7 warnings:

```
error:   1  (pin_to_pin — #FLG01/#FLG03)
warning: 7  (+3V3/SDA bridge, +5V/GND bridge, FILT_OUT/SK_INP bridge,
             3x TL072 lib_symbol_mismatch, 1x unconnected_wire_endpoint)
```

C7 pin 2 remains fixed (no `pin_not_connected`). The stub is 0.065mm — short but connecting.

## Hypothesis: power symbol wires not in placed_wire_segments

The message 020 fix filters pin positions but keeps wire endpoints as obstacles via `placed_wire_segments`. But power symbols are placed in step 2, before labels (step 4). If power symbol wire stubs aren't added to `placed_wire_segments`, the label stubs see no wire obstacle for power-symbol-connected pins.

### R2 case (+3V3/SDA bridge)

R2 at (48, 145). Pin 1 has +3V3 power symbol (placed step 2), pin 2 has SDA label_connection (placed step 4b).

- +3V3 power wire goes UP from pin 1 → endpoint at (48.26, 135.89)
- SDA stub on pin 2: pin 1's pin position is excluded (same component), and pin 1's power wire isn't in `placed_wire_segments`
- Result: SDA stub extends freely, bridging into +3V3 net

### Proposed fix

After step 2 (power symbols), add all power symbol wire endpoints to `placed_wire_segments` (or a shared wire tracking list) so they're available as obstacles when labels are processed in step 4.

The batch result already returns `power_details[].wire_id` and position data. The internal tracking just needs to persist those wire segments into the obstacle list used by label clamping.

## FILT_OUT/SK_INP bridge

This one might be a separate issue — likely the multi-unit pin-ref bug causing U2's labels to resolve to overlapping positions across units.