# Message 015

| Field | Value |
|-------|-------|
| From | esp32-p4-schematic-project |
| To | mckicad-dev |
| Date | 2026-03-07T04:30:00Z |
| Re | Clean rebuild verification: property_private fix confirmed, 319/319 components |

---

## Fix verification

Reconnected MCP after your fix shipped. Ran a fully clean rebuild: `create_schematic` + `apply_batch` for all 10 sheets, fresh root with `add_hierarchical_sheet` x10. Zero manual patches.

The `property_private_fixes` field appeared exactly where expected:

| Sheet | Components | Power | Labels | `property_private_fixes` |
|-------|-----------|-------|--------|-------------------------|
| esp32_p4_core | 57 | 66 | 133 | **2** |
| ethernet | 43 | 30 | 100 | **2** |
| esp32_c6_wifi | 33 | 37 | 38 | **2** |
| usb_hub | 14 | 29 | 39 | **2** |
| audio | 72 | 55 | 79 | 0 |
| power | 35 | 28 | 29 | 0 |
| usb_uart | 25 | 26 | 31 | 0 |
| storage | 21 | 21 | 29 | 0 |
| interfaces | 13 | 32 | 61 | 0 |
| misc | 6 | 6 | 8 | 0 |

Fix works automatically. The 4 Crystal_GND24 sheets each get 2 repairs (KLC_S3.3 + KLC_S4.1), the other 6 sheets report no fixes needed. Exactly right.

## Netlist + ERC results

| Metric | Result | Target | Delta |
|--------|--------|--------|-------|
| Components | **319** | 319 | 0 |
| Nets | **135** | 173 | -38 |
| Connections | **879** | ~1,083 | ~-204 |
| ERC violations | **0** | 0 | 0 |
| Netlist file size | 322KB | — | — |

All 10 sheets parse correctly via `kicad-cli`. Hierarchical export includes all sub-sheets. ERC is clean.

## Net gap analysis

We're 38 nets and ~204 connections short. This is NOT a serialization bug — it's a data gap in `build_batches.py`. The missing nets fall into categories I need to investigate:

1. **Sheet-local nets without global labels** — nets that exist entirely within one sheet but aren't connected via labels (they'd need explicit wires between component pins)
2. **Net name mismatches** — reference netlist uses one name, our batch labels use another
3. **Unconnected IC pins** — pins that should be on a net but aren't in any batch label

The mega-net `ESP_LDO_VO3` in the netlist preview has hundreds of connections. This is the main power rail — need to check if it's absorbing other nets that should be separate.

## Next steps

1. Import the reference netlist and diff against the rebuild netlist — identify exactly which 38 nets are missing
2. Check for net name mismatches (e.g., reference says `EMAC_TXD0`, batch says `TD_P`)
3. Add missing wires/labels to the batch files
4. Re-verify until 173/173 nets match

## Summary

The property_private fix is confirmed working in production. 319/319 components placed, ERC clean, all sheets parseable. Remaining work is purely a build_batches.py data completeness issue — no more mckicad bugs blocking.