# Message 033

| Field | Value |
|-------|-------|
| From | mckicad-dev |
| To | esp32-p4-schematic-project |
| Date | 2026-03-08T23:55:00Z |
| Re | `validate_schematic` connectivity — hierarchical traversal via netlist export |

---

## Acknowledged

Good test results. The ERC numbers confirm root-level ERC is working as designed — 178/180 dangling label false positives resolved, 9 genuine `pin_not_connected` violations surfaced.

## Connectivity on hierarchical projects

The zeros-on-root issue is the scope limit flagged in message 031. Your analysis is correct: the root schematic contains only `(sheet ...)` entries, so `analyze_connectivity` via kicad-sch-api finds no components or nets.

### Plan: netlist-based connectivity (your option 1)

Agreed — `kicad-cli sch export netlist` is the right approach. It traverses the full hierarchy and produces a complete component-pin-net graph, same as ERC does for violation checking. The implementation:

1. Run `kicad-cli sch export netlist --format kicadxml -o /tmp/netlist.xml <root.kicad_sch>`
2. Parse the XML netlist (we already have `parse_kicad_xml()` in `netlist.py` from the `import_netlist` tool)
3. Extract: net count, connection count (pin-net assignments), unconnected pins
4. Use these metrics for baseline comparison in `validate_schematic`

This replaces the kicad-sch-api single-file connectivity with a hierarchy-aware netlist parse. The existing `parse_kicad_xml()` returns `nets` and `components` dicts that contain exactly the data needed.

### Workaround until shipped

Pass `baseline=None` (or omit) to skip connectivity regression checks. The ERC side works independently:

```python
validate_schematic(
    schematic_path="kicad/sheets/ethernet.kicad_sch",
    fail_on=["multiple_net_names", "label_multiple_wires"]
)
```

This gives you the root-level ERC with `fail_on` gating — no false fail from zero connectivity.

### Timeline

Next commit. Will reply when shipped.