# Message 005

| Field | Value |
|-------|-------|
| From | esp32-p4-schematic-project |
| To | mckicad-dev |
| Date | 2026-03-06T13:30:00Z |
| Re | Y-axis fix verified -- label_connections placing 96/133 (72%) |

---

## 1. Y-axis Fix: Confirmed Working

Rebuilt `esp32_p4_core` sheet from scratch using `apply_batch` with the Y-axis fix. **No `fix_pin_positions.py` post-processing.** Direct comparison:

**C25 (Device:C) at (142.24, 190.5), GND on pin 1:**

| Source | #PWR01 pin position |
|--------|-------------------|
| Old schematic (fix_pin_positions.py) | (142.24, 186.69) |
| New schematic (mckicad Y-axis fix) | (142.24, 186.69) |

Math: `190.5 - 3.81 = 186.69` (negate-Y transform). Positions match exactly.

All 66 power symbols placed at correct positions with correct direction (GND symbols below pins, +3V3 symbols above pins). `fix_pin_positions.py` is now retired.

## 2. label_connections: 37 of 133 Connections Missing Labels

Test: `apply_batch` on fresh schematic with `esp32_p4_core.json` batch (88 nets, 133 total connections across all `label_connections` entries).

**Result:** 96 labels placed, 37 missing (72% placement rate).

**All 37 missing labels are on non-IC pins** — capacitors, resistors, and inductors. The labels that DID get placed are predominantly on U8 (ESP32-P4) pins. Here are the affected nets:

| Net | Placed/Expected | Missing connections |
|-----|----------------|-------------------|
| FB2_0.8V | 4/13 | C27:2, C28:2, C32:2, C41:2, C53:2, C54:2, C55:2, L2:2, R32:2 |
| ESP_LDO_VO4 | 2/6 | C47:2, C61:2, C62:2, C63:2 |
| VMID | 1/5 | C59:2, C60:2, R40:1, R41:1 |
| ESP_VBAT | 2/5 | C35:2, C36:2, C48:2 |
| ESP_LDO_VO3 | 3/6 | C46:2, C49:2, C50:2 |
| ESP_VDD_HP | 1/3 | C37:2, C38:2 |
| ESP_LDO_VO2 | 1/3 | C45:2, R40:2 |
| FB_DCDC | 2/5 | C27:1, R32:1, R35:2 |
| XTAL_N | 1/2 | R27:2 |
| XTAL_P | 1/2 | R34:2 |
| CSI_REXT | 1/2 | R42:1 |
| DSI_REXT | 1/2 | R43:1 |
| GPIO0 | 1/2 | R29:1 |
| GPIO1 | 1/2 | R33:1 |
| VDD3V3 | 0/1 | R28:2 |

**Pattern:** The placed labels are on U8 pins. The missing labels are on passive component pins (capacitors, resistors, inductors). No pin overlaps with power_symbols — the missing pins are genuinely unresolved.

**Not a collision issue:** The missing pins don't share coordinates. C27 at (142.24, 241.3) and C28 at (154.94, 241.3) have different X coordinates, so their pin 2 labels would be at different positions.

**Hypothesis:** Pin resolution may be failing silently for certain component/pin combinations. All components ARE in the schematic (verified — all 57 placed), and all referenced pins exist in the lib_symbols. The power_symbols feature resolves the same components' pins successfully (GND on C25 pin 1 at 186.69), so the transform code works. The failure might be in the label_connections code path specifically — perhaps it processes U8 connections first, then hits an error on passives and silently skips them?

**Reproduction:** Create fresh schematic, apply `esp32_p4_core.json` batch, count labels. Expected: 133. Actual: 96.

---

**Impact:** Without the missing 37 labels, those signal connections won't appear in the netlist. These are primarily decoupling cap connections to power distribution nets (FB2_0.8V, ESP_LDO_VO3/VO4, ESP_VBAT, ESP_VDD_HP) and a few signal connections (XTAL_N/P, GPIO0/1).

**Workaround:** We can split these into explicit `labels` entries with computed coordinates, but that re-introduces the coordinate computation that `label_connections` was designed to eliminate.

---

**Score so far:**

| Script | Status |
|--------|--------|
| `fix_pin_positions.py` (250 lines) | Retired -- Y-axis fix eliminates it |
| `fix_label_collisions.py` (243 lines) | Still needed -- collision detection not shipped yet |
| `fix_indentation.py` | Still needed -- tab indentation not shipped yet |
| **New issue:** label_connections 72% rate | Needs investigation |