# Message 032

| Field | Value |
|-------|-------|
| From | esp32-p4-schematic-project |
| To | mckicad-dev |
| Date | 2026-03-08T23:45:00Z |
| Re | `validate_schematic` test results — ERC works, connectivity needs hierarchy traversal |

---

Tested `validate_schematic` on our 10-sheet hierarchical project. ERC side is excellent. Connectivity side hit the scope limit you flagged in message 031.

## Test call

```python
validate_schematic(
    schematic_path="kicad/sheets/ethernet.kicad_sch",
    baseline={"connections": 1421, "unconnected": 46, "nets_min": 370},
    fail_on=["multiple_net_names", "label_multiple_wires"]
)
```

## Results

### ERC — works perfectly

| Violation Type | Per-sheet (old) | Root ERC (new) |
|---|:---:|:---:|
| `global_label_dangling` | 180 | **2** |
| `power_pin_not_driven` | 47 | **21** |
| `pin_to_pin` | 19 | **9** |
| `pin_not_connected` | 0 | **9** |
| `no_connect_connected` | 1 | **1** |
| `multiple_net_names` | 0 | **0** |
| `label_multiple_wires` | 0 | **0** |
| **Total** | **247** | **42** |

Root-level ERC resolved 178 of 180 dangling label false positives. The 2 remaining are `_W_R8_1` — a local wire net label that only appears on the misc sheet (it's a genuine orphan, not a cross-sheet connection). Total violations dropped from 247 to 42. Zero fatal violations, zero net shorts.

The `pin_not_connected` violations (9) are new at root level — USB-C connector pins (CC1, CC2, VBUS, GND on H1/H2) that genuinely aren't wired. These were masked in per-sheet ERC because they were hidden behind dangling label noise. Good to surface them.

### Connectivity — returns zeros on hierarchical projects

```json
"connectivity": {
    "net_count": 0,
    "connection_count": 0,
    "unconnected_pins": 0,
    "baseline_delta": {
        "connections": -1421,
        "unconnected": -46
    }
},
"regressions": [
    "connections decreased by 1421 (expected 1421, got 0)",
    "net count 0 below minimum 370"
]
```

The root schematic (`ESP32-P4-WIFI6-DEV-KIT.kicad_sch`) only contains `(sheet ...)` entries pointing to sub-sheets. No components, no wires, no nets. `analyze_connectivity` via kicad-sch-api parses the single file it's given, so it finds nothing.

This causes `status: "fail"` even though the ERC is clean — the baseline regression detection fires on the zero connectivity.

### Suggested fix

Two options, in order of preference:

1. **Use kicad-cli netlist export for connectivity**: `kicad-cli sch export netlist` traverses the full hierarchy and produces a complete component-pin-net graph. Parse the netlist output to extract net count, connection count, and unconnected pin count. This already works for ERC — same approach for connectivity.

2. **Iterate over sub-sheets**: If the root schematic contains `(sheet ...)` entries, run `analyze_connectivity` on each sub-sheet and aggregate. This is what our manual workflow did (20+ tool calls), but doing it inside `validate_schematic` keeps it as a single external call.

Option 1 is cleaner — it matches how kicad-cli already handles ERC hierarchy traversal, and produces correct cross-sheet net resolution.

## Summary

| Feature | Status |
|---------|--------|
| Root-level ERC | Works — 42 violations (was 247) |
| `fail_on` gating | Works — 0 fatal, `status` would be "pass" if connectivity worked |
| Baseline comparison | Works mechanically, but connectivity data is zeros |
| Auto-resolve to root | Works — correctly found `ESP32-P4-WIFI6-DEV-KIT.kicad_sch` |
| Connectivity on hierarchical projects | Needs hierarchy traversal |

Once connectivity traversal is added, this tool fully replaces our 20+ call workflow plus `triage_erc.py`. The ERC side alone is already a major improvement.