Fix CE amp coupling cap routing and Colpitts test variable selection
CE amplifier schematic: the input coupling cap CC_in was placed horizontally (R90) at y=336 — the same y as the RB1-to-base bias wire. Both cap pins sat on the wire, shorting the cap and allowing Vin's 0V DC to override the bias divider, putting Q1 in cutoff. Fix: move CC_in to vertical orientation (R0) above the base wire. Now pinA=(400,256) and pinB=(400,320) are off the y=336 bias path. The cap properly blocks DC while passing the 1kHz input signal. Result: V(out) swings 2.2Vpp (gain ≈ 110) instead of stuck at Vcc. Colpitts oscillator test: the schematic was actually working (V(out) pp=2.05V) but the test's fallback variable selection picked V(n001) (the Vcc rail, constant 12V) instead of V(out). Fix: look for V(out) first since the schematic labels the collector with "out". Integration tests: 4/4 pass, unit tests: 360/360 pass.
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@ -581,76 +581,70 @@ def generate_common_emitter_amp(
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qe = pin_position("npn", 2, 400, 288) # emitter
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# RC from Vcc rail to collector.
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# Want pinB at collector (464, 288). res at (448, 192): pinB=(464, 288). Good.
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# res at (448, 192): pinA=(464, 208)=vcc rail, pinB=(464, 288)=collector
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rc_a = pin_position("res", 0, 448, 192) # (464, 208) = vcc rail
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# RE from emitter to GND.
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# Want pinA at emitter (464, 384). res at (448, 368): pinA=(464, 384).
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# res at (448, 368): pinA=(464, 384)=emitter, pinB=(464, 464)=GND
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re_b = pin_position("res", 1, 448, 368) # (464, 464) = GND
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# RB1 from Vcc rail to base. Vertical, placed to the left of Q1.
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# Want pinB at base Y (336). res at (240, 240): pinA=(256, 256), pinB=(256, 336)
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# RB1 from Vcc rail to base. res at (240, 240): pinA=(256, 256), pinB=(256, 336)
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rb1_a = pin_position("res", 0, 240, 240) # (256, 256)
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rb1_b = pin_position("res", 1, 240, 240) # (256, 336)
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# RB2 from base to GND.
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# Want pinA at base Y (336). res at (240, 320): pinA=(256, 336), pinB=(256, 416)
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# RB2 from base to GND. res at (240, 320): pinA=(256, 336), pinB=(256, 416)
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rb2_b = pin_position("res", 1, 240, 320) # (256, 416)
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# CC_in (input coupling cap) horizontal, connecting input to base.
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# cap R90: pinA=origin+(-16,0)→(origin_x, origin_y+16)... wait let me recalculate.
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# cap R90: pinA offset (16,0) → rotate90 → (0, 16), pinB offset (16,64) → (-64, 16)
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# At origin (368, 320): pinA = (368, 336), pinB = (304, 336)
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# pinA at (368, 336) close to base (400, 336). pinB at (304, 336).
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# Wire from pinA (368, 336) to base (400, 336).
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ccin_a = pin_position("cap", 0, 368, 320, 90) # (368, 336)
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ccin_b = pin_position("cap", 1, 368, 320, 90) # (304, 336)
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# CC_in (input coupling cap) — VERTICAL (R0) above the base wire.
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# cap R0 at (384, 256): pinA=(400, 256)=input side, pinB=(400, 320)=base side.
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# Critically, neither pin sits on the horizontal RB1-to-base wire at y=336,
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# so the coupling cap is NOT shorted by the bias wire.
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ccin_a = pin_position("cap", 0, 384, 256) # (400, 256) = input
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ccin_b = pin_position("cap", 1, 384, 256) # (400, 320) = base side
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# CC_out (output coupling cap) to the right of collector.
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# cap R90 at origin (560, 272): pinA = (560, 288), pinB = (496, 288)
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# pinB near collector (464, 288), pinA extends right to output
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# Actually pinB = (560-64, 288) = (496, 288). Wire from collector (464,288) to (496,288).
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# CC_out (output coupling cap) horizontal R90 to the right of collector.
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# cap R90 at (560, 272): pinA=(560, 288)=output, pinB=(496, 288)=collector side
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ccout_a = pin_position("cap", 0, 560, 272, 90) # (560, 288)
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ccout_b = pin_position("cap", 1, 560, 272, 90) # (496, 288)
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# CE (emitter bypass cap) parallel to RE.
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# Place to the right of RE. cap at (528, 384): pinA=(544, 384), pinB=(544, 448)
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# cap at (528, 384): pinA=(544, 384)=emitter, pinB=(544, 448)=GND
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ce_a = pin_position("cap", 0, 528, 384) # (544, 384)
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ce_b = pin_position("cap", 1, 528, 384) # (544, 448)
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# Vcc source at (80, 96): pin+=(80, 112), pin-=(80, 192)
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# Vcc source at (80, 96): pin+=(80, 112), pin-=(80, 192)
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vcc_p = pin_position("voltage", 0, 80, 96) # (80, 112)
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vcc_n = pin_position("voltage", 1, 80, 96) # (80, 192)
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# Vin source at (80, 288): pin+=(80, 304), pin-=(80, 384)
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# Vin source at (80, 288): pin+=(80, 304), pin-=(80, 384)
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vin_p = pin_position("voltage", 0, 80, 288) # (80, 304)
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vin_n = pin_position("voltage", 1, 80, 288) # (80, 384)
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# === WIRING ===
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# Vcc rail at y=208 — route RIGHT from Vcc+ first (avoid crossing Vcc- at 80,192)
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# Vcc rail at y=208 — route RIGHT from Vcc+ (avoid crossing Vcc- at 80,192)
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vcc_y = rc_a[1] # 208
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sch.add_wire(vcc_p[0], vcc_p[1], 160, vcc_p[1]) # (80,112) → (160,112)
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sch.add_wire(160, vcc_p[1], 160, vcc_y) # (160,112) → (160,208)
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sch.add_wire(160, vcc_y, rc_a[0], vcc_y) # (160,208) → (464,208) = RC top
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sch.add_wire(rb1_a[0], rb1_a[1], rb1_a[0], vcc_y) # RB1 top up to rail
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sch.add_wire(rb1_a[0], vcc_y, rc_a[0], vcc_y) # connect to rail
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sch.add_wire(vcc_p[0], vcc_p[1], 160, vcc_p[1]) # (80,112)→(160,112)
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sch.add_wire(160, vcc_p[1], 160, vcc_y) # (160,112)→(160,208)
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sch.add_wire(160, vcc_y, rc_a[0], vcc_y) # (160,208)→(464,208) = RC top
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sch.add_wire(rb1_a[0], rb1_a[1], rb1_a[0], vcc_y) # RB1 top up to rail
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sch.add_wire(rb1_a[0], vcc_y, rc_a[0], vcc_y) # connect to rail
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# RB1 bottom to base, RB2 top at same junction
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sch.add_wire(rb1_b[0], rb1_b[1], qb[0], qb[1]) # RB1 bottom → base
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# RB1 bottom → base (horizontal at y=336)
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sch.add_wire(rb1_b[0], rb1_b[1], qb[0], qb[1])
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# CC_in to base
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sch.add_wire(ccin_a[0], ccin_a[1], qb[0], qb[1]) # CC_in right → base
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# CC_in base side → base junction (short vertical drop)
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sch.add_wire(ccin_b[0], ccin_b[1], qb[0], qb[1]) # (400,320)→(400,336)
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# Input: Vin+ to CC_in left
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sch.add_wire(vin_p[0], vin_p[1], ccin_b[0], ccin_b[1]) # Vin+ → CC_in left
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# Vin+ → CC_in input side via manhattan L-route
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sch.add_wire(vin_p[0], vin_p[1], ccin_a[0], vin_p[1]) # (80,304)→(400,304)
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sch.add_wire(ccin_a[0], vin_p[1], ccin_a[0], ccin_a[1]) # (400,304)→(400,256)
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# Collector to CC_out
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sch.add_wire(qc[0], qc[1], ccout_b[0], ccout_b[1]) # collector → CC_out left
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# Collector → CC_out left pin
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sch.add_wire(qc[0], qc[1], ccout_b[0], ccout_b[1])
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# Emitter to CE (bypass cap in parallel with RE)
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sch.add_wire(qe[0], qe[1], ce_a[0], ce_a[1]) # emitter → CE top
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# CE bottom to RE bottom (shared GND rail)
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sch.add_wire(ce_b[0], ce_b[1], re_b[0], re_b[1]) # CE bot → RE bot
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# Emitter → CE top (bypass cap in parallel with RE)
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sch.add_wire(qe[0], qe[1], ce_a[0], ce_a[1])
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# CE bottom → GND (separate ground flag, no diagonal wire to RE)
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# === COMPONENTS ===
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sch.add_component("npn", "Q1", bjt_model, 400, 288)
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@ -658,7 +652,7 @@ def generate_common_emitter_amp(
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sch.add_component("res", "RE", re, 448, 368)
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sch.add_component("res", "RB1", rb1, 240, 240)
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sch.add_component("res", "RB2", rb2, 240, 320)
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sch.add_component("cap", "CC1", cc_in, 368, 320, rotation=90)
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sch.add_component("cap", "CC1", cc_in, 384, 256)
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sch.add_component("cap", "CC2", cc_out, 560, 272, rotation=90)
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sch.add_component("cap", "CE", ce, 528, 384)
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sch.add_component("voltage", "Vcc", vcc, 80, 96)
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@ -669,6 +663,7 @@ def generate_common_emitter_amp(
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sch.add_ground(*vin_n)
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sch.add_ground(*rb2_b)
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sch.add_ground(*re_b)
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sch.add_ground(*ce_b) # CE bottom to GND directly (no diagonal wire)
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sch.add_net_label("out", *ccout_a)
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sch.add_directive(".tran 5m", 80, 528)
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@ -180,28 +180,19 @@ class TestColpittsOscillator:
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raw = result.raw_data
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time_idx = None
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# Look for collector voltage
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vcol_idx = None
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for var in raw.variables:
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if var.name.lower() == "time":
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time_idx = var.index
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elif "collector" in var.name.lower() or var.name.lower() == "v(collector)":
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elif var.name.lower() == "v(out)":
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vcol_idx = var.index
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elif "collector" in var.name.lower() and vcol_idx is None:
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vcol_idx = var.index
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assert time_idx is not None
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if vcol_idx is None:
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# Fall back to any voltage signal that isn't supply
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for var in raw.variables:
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if var.name.lower().startswith("v(") and var.name.lower() not in (
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"v(vcc)",
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"v(time)",
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):
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vcol_idx = var.index
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break
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assert vcol_idx is not None, (
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f"No suitable signal found. Variables: {[v.name for v in raw.variables]}"
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f"No V(out) or collector signal. Variables: {[v.name for v in raw.variables]}"
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)
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sig = np.real(raw.data[vcol_idx])
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