Ryan Malloy
b16c20c2ca
CE amplifier schematic: the input coupling cap CC_in was placed horizontally (R90) at y=336 — the same y as the RB1-to-base bias wire. Both cap pins sat on the wire, shorting the cap and allowing Vin's 0V DC to override the bias divider, putting Q1 in cutoff. Fix: move CC_in to vertical orientation (R0) above the base wire. Now pinA=(400,256) and pinB=(400,320) are off the y=336 bias path. The cap properly blocks DC while passing the 1kHz input signal. Result: V(out) swings 2.2Vpp (gain ≈ 110) instead of stuck at Vcc. Colpitts oscillator test: the schematic was actually working (V(out) pp=2.05V) but the test's fallback variable selection picked V(n001) (the Vcc rail, constant 12V) instead of V(out). Fix: look for V(out) first since the schematic labels the collector with "out". Integration tests: 4/4 pass, unit tests: 360/360 pass.
210 lines
7.7 KiB
Python
210 lines
7.7 KiB
Python
"""Integration tests that run actual LTspice simulations.
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These tests require LTspice and Wine to be installed. Skip with:
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pytest -m 'not integration'
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"""
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import tempfile
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from pathlib import Path
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import numpy as np
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import pytest
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from mcp_ltspice.asc_generator import (
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generate_colpitts_oscillator as generate_colpitts_asc,
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)
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from mcp_ltspice.asc_generator import (
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generate_common_emitter_amp as generate_ce_amp_asc,
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)
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from mcp_ltspice.asc_generator import (
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generate_non_inverting_amp as generate_noninv_amp_asc,
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)
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from mcp_ltspice.asc_generator import (
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generate_rc_lowpass as generate_rc_lowpass_asc,
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)
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from mcp_ltspice.runner import run_simulation
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from mcp_ltspice.waveform_math import compute_bandwidth, compute_rms
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@pytest.mark.integration
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class TestRCLowpass:
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"""End-to-end test: RC lowpass filter -> simulate -> verify -3dB point."""
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async def test_rc_lowpass_bandwidth(self, ltspice_available):
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"""Generate RC lowpass (R=1k, C=100n), simulate, verify fc ~ 1.6 kHz."""
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# Generate schematic
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sch = generate_rc_lowpass_asc(r="1k", c="100n")
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with tempfile.TemporaryDirectory() as tmpdir:
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asc_path = Path(tmpdir) / "rc_lowpass.asc"
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sch.save(asc_path)
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# Simulate
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result = await run_simulation(asc_path)
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assert result.success, f"Simulation failed: {result.error or result.stderr}"
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assert result.raw_data is not None, "No raw data produced"
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# Find frequency and V(out) variables
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raw = result.raw_data
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freq_idx = None
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vout_idx = None
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for var in raw.variables:
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if var.name.lower() == "frequency":
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freq_idx = var.index
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elif var.name.lower() == "v(out)":
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vout_idx = var.index
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assert freq_idx is not None, (
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f"No frequency variable. Variables: {[v.name for v in raw.variables]}"
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)
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assert vout_idx is not None, (
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f"No V(out) variable. Variables: {[v.name for v in raw.variables]}"
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)
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# Extract data
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freq = np.abs(raw.data[freq_idx])
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mag_complex = raw.data[vout_idx]
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mag_db = 20.0 * np.log10(np.maximum(np.abs(mag_complex), 1e-30))
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# Compute bandwidth
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bw = compute_bandwidth(freq, mag_db)
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# Expected: fc = 1/(2*pi*1000*100e-9) ~ 1591 Hz
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# Allow 20% tolerance for simulation differences
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expected_fc = 1.0 / (2 * np.pi * 1000 * 100e-9)
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assert bw["bandwidth_hz"] is not None, "Could not compute bandwidth"
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assert abs(bw["bandwidth_hz"] - expected_fc) / expected_fc < 0.2, (
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f"Bandwidth {bw['bandwidth_hz']:.0f} Hz too far from expected {expected_fc:.0f} Hz"
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)
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@pytest.mark.integration
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class TestNonInvertingAmp:
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"""End-to-end test: non-inverting amp -> simulate -> verify gain."""
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async def test_noninv_amp_gain(self, ltspice_available):
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"""Generate non-inverting amp (Rf=100k, Rin=10k), verify gain ~ 11 (20.8 dB)."""
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sch = generate_noninv_amp_asc(rin="10k", rf="100k")
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with tempfile.TemporaryDirectory() as tmpdir:
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asc_path = Path(tmpdir) / "noninv_amp.asc"
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sch.save(asc_path)
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result = await run_simulation(asc_path)
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assert result.success, f"Simulation failed: {result.error or result.stderr}"
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assert result.raw_data is not None
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raw = result.raw_data
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freq_idx = None
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vout_idx = None
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for var in raw.variables:
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if var.name.lower() == "frequency":
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freq_idx = var.index
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elif var.name.lower() == "v(out)":
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vout_idx = var.index
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assert freq_idx is not None
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assert vout_idx is not None
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_freq = np.abs(raw.data[freq_idx]) # noqa: F841 — kept for debug
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mag = np.abs(raw.data[vout_idx])
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mag_db = 20.0 * np.log10(np.maximum(mag, 1e-30))
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# At low frequency, gain should be 1 + 100k/10k = 11 = 20.83 dB
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# Use first few points (low frequency)
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low_freq_gain_db = float(np.mean(mag_db[:5]))
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expected_gain_db = 20 * np.log10(11) # 20.83 dB
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assert abs(low_freq_gain_db - expected_gain_db) < 2.0, (
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f"Low-freq gain {low_freq_gain_db:.1f} dB, expected ~{expected_gain_db:.1f} dB"
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)
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@pytest.mark.integration
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class TestCommonEmitterAmp:
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"""End-to-end test: CE amplifier -> simulate transient -> verify output exists."""
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async def test_ce_amp_output(self, ltspice_available):
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"""Generate CE amp, simulate transient, verify output has AC content."""
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sch = generate_ce_amp_asc()
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with tempfile.TemporaryDirectory() as tmpdir:
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asc_path = Path(tmpdir) / "ce_amp.asc"
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sch.save(asc_path)
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result = await run_simulation(asc_path)
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assert result.success, f"Simulation failed: {result.error or result.stderr}"
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assert result.raw_data is not None
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raw = result.raw_data
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time_idx = None
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vout_idx = None
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for var in raw.variables:
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if var.name.lower() == "time":
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time_idx = var.index
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elif var.name.lower() == "v(out)":
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vout_idx = var.index
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assert time_idx is not None
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assert vout_idx is not None
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sig = np.real(raw.data[vout_idx])
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# Output should not be DC-only -- check peak-to-peak > threshold
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pp = float(np.max(sig) - np.min(sig))
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assert pp > 0.01, (
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f"Output appears DC-only (peak-to-peak={pp:.4f}V). "
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"Expected amplified AC signal."
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)
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# RMS should be non-trivial
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rms = float(compute_rms(sig))
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assert rms > 0.01, f"Output RMS too low: {rms:.4f}V"
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@pytest.mark.integration
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class TestColpittsOscillator:
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"""End-to-end test: Colpitts oscillator -> simulate -> verify oscillation."""
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async def test_colpitts_oscillation(self, ltspice_available):
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"""Generate Colpitts oscillator, verify oscillation near expected frequency."""
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sch = generate_colpitts_asc()
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with tempfile.TemporaryDirectory() as tmpdir:
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asc_path = Path(tmpdir) / "colpitts.asc"
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sch.save(asc_path)
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result = await run_simulation(asc_path)
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assert result.success, f"Simulation failed: {result.error or result.stderr}"
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assert result.raw_data is not None
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raw = result.raw_data
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time_idx = None
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vcol_idx = None
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for var in raw.variables:
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if var.name.lower() == "time":
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time_idx = var.index
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elif var.name.lower() == "v(out)":
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vcol_idx = var.index
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elif "collector" in var.name.lower() and vcol_idx is None:
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vcol_idx = var.index
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assert time_idx is not None
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assert vcol_idx is not None, (
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f"No V(out) or collector signal. Variables: {[v.name for v in raw.variables]}"
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)
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sig = np.real(raw.data[vcol_idx])
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# Oscillator output should have significant AC content
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pp = float(np.max(sig) - np.min(sig))
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assert pp > 0.1, (
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f"Output peak-to-peak {pp:.3f}V too small -- oscillator may not have started"
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)
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# Expected frequency: f = 1/(2*pi*sqrt(L*C1*C2/(C1+C2)))
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# With L=1u, C1=C2=100p: Cseries = 50p
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# f = 1/(2*pi*sqrt(1e-6 * 50e-12)) ~ 22.5 MHz
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# This is quite high, but we just verify oscillation exists
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