Ryan Malloy
d2d33fff57
The .asc schematic templates had wrong pin offsets, causing LTspice to extract netlists with disconnected (NC_*) nodes and singular matrix errors. Fixed by reading pin positions from the .asy symbol files and applying the correct CCW rotation transform: R90 maps (px, py) → (-py, px). Pin offsets: voltage (+0,+16)/(+0,+96), res (+16,+16)/(+16,+96), cap (+16,+0)/(+16,+64). Added pin_position() helper and _PIN_OFFSETS table for reuse by all layout functions. Verified end-to-end: generate_rc_lowpass → simulate → bandwidth gives 1587.8 Hz vs theoretical 1591.5 Hz (0.24% error).
379 lines
12 KiB
Python
379 lines
12 KiB
Python
"""Programmatic LTspice .asc schematic file generation.
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Generates graphical schematics (the .asc format LTspice uses for its GUI),
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not just text netlists. Components are placed using absolute pin positions
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derived from the .asy symbol files and rotated with the standard CCW
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transform: R90 applies (px, py) → (-py, px) relative to the component origin.
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"""
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from __future__ import annotations
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from dataclasses import dataclass, field
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from pathlib import Path
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# LTspice grid spacing -- all coordinates should be multiples of this
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GRID = 80
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# Pin positions (relative to component origin) from LTspice .asy files.
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# R0 orientation. Key = symbol name, value = list of (px, py) per pin.
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_PIN_OFFSETS: dict[str, list[tuple[int, int]]] = {
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"voltage": [(0, 16), (0, 96)], # pin+ , pin-
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"res": [(16, 16), (16, 96)], # pinA , pinB
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"cap": [(16, 0), (16, 64)], # pinA , pinB
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"ind": [(16, 16), (16, 96)], # pinA , pinB (same body as res)
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}
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def _rotate(px: int, py: int, rotation: int) -> tuple[int, int]:
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"""Apply LTspice rotation to a relative pin offset.
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LTspice rotations are counterclockwise: (px, py) → (-py, px) for R90.
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"""
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if rotation == 0:
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return px, py
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if rotation == 90:
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return -py, px
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if rotation == 180:
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return -px, -py
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if rotation == 270:
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return py, -px
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return px, py
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def pin_position(
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symbol: str, pin_index: int, cx: int, cy: int, rotation: int = 0
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) -> tuple[int, int]:
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"""Compute absolute pin position for a component.
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Args:
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symbol: Base symbol name (``"res"``, ``"cap"``, ``"voltage"``, ...)
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pin_index: 0 for first pin, 1 for second pin, etc.
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cx: Component origin X
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cy: Component origin Y
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rotation: 0, 90, 180, or 270
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Returns:
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Absolute (x, y) of the pin.
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"""
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offsets = _PIN_OFFSETS.get(symbol, [(0, 0), (0, 80)])
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px, py = offsets[pin_index % len(offsets)]
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rx, ry = _rotate(px, py, rotation)
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return cx + rx, cy + ry
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@dataclass
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class _WireEntry:
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x1: int
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y1: int
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x2: int
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y2: int
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@dataclass
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class _SymbolEntry:
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symbol: str
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name: str
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value: str
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x: int
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y: int
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rotation: int # 0, 90, 180, 270
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windows: list[str] = field(default_factory=list)
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@dataclass
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class _FlagEntry:
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x: int
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y: int
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name: str
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@dataclass
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class _TextEntry:
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x: int
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y: int
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content: str
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class AscSchematic:
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"""Builder for LTspice .asc schematic files.
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All ``add_*`` methods return ``self`` for chaining::
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sch = (AscSchematic()
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.add_component("res", "R1", "1k", 160, 176, rotation=90)
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.add_wire(80, 176, 160, 176)
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.add_ground(80, 256))
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"""
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def __init__(self, sheet_w: int = 880, sheet_h: int = 680) -> None:
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self._sheet_w = sheet_w
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self._sheet_h = sheet_h
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self._wires: list[_WireEntry] = []
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self._symbols: list[_SymbolEntry] = []
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self._flags: list[_FlagEntry] = []
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self._texts: list[_TextEntry] = []
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# -- builder methods -----------------------------------------------------
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def add_component(
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self,
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symbol: str,
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name: str,
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value: str,
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x: int,
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y: int,
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rotation: int = 0,
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) -> AscSchematic:
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"""Place a component symbol.
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Args:
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symbol: LTspice symbol name (``res``, ``cap``, ``voltage``, etc.)
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name: Instance name (``R1``, ``C1``, ``V1``, ...)
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value: Component value (``1k``, ``100n``, ``AC 1``, ...)
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x: X coordinate (should be on 80-pixel grid)
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y: Y coordinate
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rotation: 0, 90, 180, or 270 degrees
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"""
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windows: list[str] = []
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# For resistors and inductors placed at R90, shift the WINDOW lines
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# so labels sit neatly above/below the body
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if rotation == 90 and symbol in ("res", "ind", "ind2"):
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windows = [
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"WINDOW 0 0 56 VBottom 2",
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"WINDOW 3 32 56 VTop 2",
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]
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self._symbols.append(_SymbolEntry(symbol, name, value, x, y, rotation, windows))
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return self
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def add_wire(self, x1: int, y1: int, x2: int, y2: int) -> AscSchematic:
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"""Add a wire segment between two points."""
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self._wires.append(_WireEntry(x1, y1, x2, y2))
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return self
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def add_ground(self, x: int, y: int) -> AscSchematic:
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"""Place a ground flag (net name ``0``)."""
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self._flags.append(_FlagEntry(x, y, "0"))
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return self
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def add_net_label(self, name: str, x: int, y: int) -> AscSchematic:
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"""Place a named net label (e.g., ``out``, ``vdd``)."""
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self._flags.append(_FlagEntry(x, y, name))
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return self
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def add_directive(self, text: str, x: int, y: int) -> AscSchematic:
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"""Add a SPICE directive (rendered with ``!`` prefix)."""
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self._texts.append(_TextEntry(x, y, text))
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return self
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# -- output --------------------------------------------------------------
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def render(self) -> str:
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"""Render the schematic to an ``.asc`` format string."""
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lines: list[str] = []
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lines.append("Version 4")
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lines.append(f"SHEET 1 {self._sheet_w} {self._sheet_h}")
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for w in self._wires:
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lines.append(f"WIRE {w.x1} {w.y1} {w.x2} {w.y2}")
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for f in self._flags:
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lines.append(f"FLAG {f.x} {f.y} {f.name}")
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for s in self._symbols:
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lines.append(f"SYMBOL {s.symbol} {s.x} {s.y} R{s.rotation}")
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for win in s.windows:
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lines.append(win)
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lines.append(f"SYMATTR InstName {s.name}")
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lines.append(f"SYMATTR Value {s.value}")
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for t in self._texts:
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lines.append(f"TEXT {t.x} {t.y} Left 2 !{t.content}")
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return "\n".join(lines) + "\n"
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def save(self, path: Path | str) -> Path:
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"""Write the schematic to an ``.asc`` file on disk."""
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path = Path(path)
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path.write_text(self.render(), encoding="utf-8")
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return path
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# ============================================================================
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# Layout helper functions -- auto-placed, ready-to-simulate schematics
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# ============================================================================
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def generate_rc_lowpass(r: str = "1k", c: str = "100n") -> AscSchematic:
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"""Generate an RC lowpass filter schematic with AC analysis.
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Signal flow (left to right)::
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V1 --[R1]-- out --+
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[C1]
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GND
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Args:
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r: Resistor value (e.g., ``"1k"``, ``"4.7k"``)
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c: Capacitor value (e.g., ``"100n"``, ``"10p"``)
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Returns:
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An ``AscSchematic`` ready to ``.save()`` or ``.render()``.
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"""
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sch = AscSchematic()
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# Component origins (all on 16-pixel sub-grid for pin alignment)
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# V1 at (80, 80) R0: pin+ = (80, 96), pin- = (80, 176)
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# R1 at (160, 80) R0: pinA = (176, 96), pinB = (176, 176)
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# C1 at (256, 176) R0: pinA = (272, 176), pinB = (272, 240)
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v1p = pin_position("voltage", 0, 80, 80) # (80, 96)
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v1n = pin_position("voltage", 1, 80, 80) # (80, 176)
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r1a = pin_position("res", 0, 160, 80) # (176, 96)
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r1b = pin_position("res", 1, 160, 80) # (176, 176)
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c1a = pin_position("cap", 0, 256, 176) # (272, 176)
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c1b = pin_position("cap", 1, 256, 176) # (272, 240)
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# Wires
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sch.add_wire(*v1p, *r1a) # V1+ to R1 top
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sch.add_wire(*r1b, *c1a) # R1 bottom to C1 top (junction = "out")
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# Components
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sch.add_component("voltage", "V1", "AC 1", 80, 80)
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sch.add_component("res", "R1", r, 160, 80)
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sch.add_component("cap", "C1", c, 256, 176)
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# Ground flags at V1- and C1 bottom
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sch.add_ground(*v1n)
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sch.add_ground(*c1b)
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# Output net label at the R1-C1 junction
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sch.add_net_label("out", *r1b)
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# Simulation directive
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sch.add_directive(".ac dec 100 1 1meg", 80, 296)
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return sch
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def generate_voltage_divider(
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r1: str = "10k",
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r2: str = "10k",
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vin: str = "5",
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) -> AscSchematic:
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"""Generate a voltage divider schematic with operating-point analysis.
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Topology (vertical)::
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V1+ --[R1]-- out --[R2]-- GND
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V1- = GND
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Args:
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r1: Top resistor value
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r2: Bottom resistor value
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vin: DC input voltage
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Returns:
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An ``AscSchematic`` ready to ``.save()`` or ``.render()``.
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"""
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sch = AscSchematic()
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# Vertical layout: V1 on left, R1 and R2 stacked vertically on right
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# V1 at (80, 80) R0: pin+ = (80, 96), pin- = (80, 176)
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# R1 at (176, 0) R0: pinA = (192, 16), pinB = (192, 96)
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# R2 at (176, 96) R0: pinA = (192, 112), pinB = (192, 192)
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v1p = pin_position("voltage", 0, 80, 80) # (80, 96)
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v1n = pin_position("voltage", 1, 80, 80) # (80, 176)
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r1a = pin_position("res", 0, 176, 0) # (192, 16)
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r1b = pin_position("res", 1, 176, 0) # (192, 96)
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r2a = pin_position("res", 0, 176, 96) # (192, 112)
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r2b = pin_position("res", 1, 176, 96) # (192, 192)
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# Wires: V1+ to R1 top, R1 bottom to R2 top (junction = "out")
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sch.add_wire(*v1p, *r1a) # need to connect (80,96) to (192,16)
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# Route: V1+ up then right then down to R1 top
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sch.add_wire(80, 96, 80, 16)
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sch.add_wire(80, 16, 192, 16)
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# R1 bottom to R2 top
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sch.add_wire(*r1b, *r2a)
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# Components
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sch.add_component("voltage", "V1", vin, 80, 80)
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sch.add_component("res", "R1", r1, 176, 0)
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sch.add_component("res", "R2", r2, 176, 96)
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# Ground
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sch.add_ground(*v1n)
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sch.add_ground(*r2b)
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# Net label at R1-R2 junction
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sch.add_net_label("out", *r1b)
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# Directive
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sch.add_directive(".op", 80, 240)
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return sch
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def generate_inverting_amp(
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rin: str = "10k",
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rf: str = "100k",
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opamp_model: str = "UniversalOpamp2",
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) -> AscSchematic:
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"""Generate an inverting op-amp amplifier schematic.
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Topology::
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V1 --[Rin]--> inv(-) --[Rf]--> out
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non-inv(+) --> GND
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Supply: Vpos=+15V, Vneg=-15V
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The gain is ``-Rf/Rin``.
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This template uses the netlist (.cir) builder approach for the
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op-amp since op-amp symbols have complex multi-pin layouts. The
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generated .asc is a placeholder showing the RC input network.
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Args:
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rin: Input resistor value
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rf: Feedback resistor value
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opamp_model: Op-amp symbol name (default ``UniversalOpamp2``,
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the built-in ideal op-amp that needs no external model file)
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Returns:
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An ``AscSchematic`` ready to ``.save()`` or ``.render()``.
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"""
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sch = AscSchematic(sheet_w=1200, sheet_h=880)
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# For the inverting amp, use a vertical layout with known-good pin positions.
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# V1 at (80, 160) R0: pin+ = (80, 176), pin- = (80, 256)
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# Rin at (160, 160) R0: pinA = (176, 176), pinB = (176, 256)
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# Rf at (320, 160) R0: pinA = (336, 176), pinB = (336, 256)
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v1p = pin_position("voltage", 0, 80, 160)
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v1n = pin_position("voltage", 1, 80, 160)
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rin_a = pin_position("res", 0, 160, 160)
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rin_b = pin_position("res", 1, 160, 160)
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rf_a = pin_position("res", 0, 320, 160)
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rf_b = pin_position("res", 1, 320, 160)
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# V1+ → Rin top
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sch.add_wire(*v1p, *rin_a)
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# Rin bottom → Rf top (inverting node)
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sch.add_wire(*rin_b, *rf_a)
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sch.add_component("voltage", "V1", "AC 1", 80, 160)
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sch.add_component("res", "Rin", rin, 160, 160)
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sch.add_component("res", "Rf", rf, 320, 160)
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sch.add_ground(*v1n)
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sch.add_ground(*rf_b)
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sch.add_net_label("inv", *rin_b)
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sch.add_net_label("out", *rf_a)
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sch.add_directive(".ac dec 100 1 1meg", 80, 320)
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return sch
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