warehack.ing/WireViz
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Clean up code

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This commit is contained in:
Daniel Rojas 2020-05-28 17:51:30 +02:00
parent 71641df39b
commit 07567be3ca
2 changed files with 24 additions and 27 deletions
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39
src/wireviz.py
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@ -82,38 +82,36 @@ class Harness:
dot.attr('edge', style='bold', fontname=font) dot.attr('edge', style='bold', fontname=font)
# prepare ports on connectors depending on which side they will connect # prepare ports on connectors depending on which side they will connect
for k in self.cables: for k, c in self.cables.items():
c = self.cables[k]
for x in c.connections: for x in c.connections:
if x[1] is not None: # connect to left if x[1] is not None: # connect to left
self.nodes[x[0]].ports_right = True self.nodes[x[0]].ports_right = True
if x[4] is not None: # connect to right if x[4] is not None: # connect to right
self.nodes[x[3]].ports_left = True self.nodes[x[3]].ports_left = True
for k in self.nodes: for k, n in self.nodes.items():
n = self.nodes[k]
# a = attributes # a = attributes
a = [n.type, a = [n.type,
n.gender, n.gender,
'{}-pin'.format(len(n.pinout)) if n.show_num_pins == True else ''] '{}-pin'.format(len(n.pinout)) if n.show_num_pins else '']
# p = pinout # p = pinout
p = [[],[],[]] p = [[],[],[]]
p[1] = list(n.pinout) p[1] = list(n.pinout)
for i,x in enumerate(n.pinout, 1): for i, x in enumerate(n.pinout, 1):
if n.ports_left == True: if n.ports_left:
p[0].append('<p{portno}l>{portno}'.format(portno=i)) p[0].append('<p{portno}l>{portno}'.format(portno=i))
if n.ports_right == True: if n.ports_right:
p[2].append('<p{portno}r>{portno}'.format(portno=i)) p[2].append('<p{portno}r>{portno}'.format(portno=i))
# l = label # l = label
l = [n.name if n.show_name == True else '', a, p] l = [n.name if n.show_name else '', a, p]
dot.node(k, label=nested(l)) dot.node(k, label=nested(l))
if len(n.loops) > 0: if len(n.loops) > 0:
dot.attr('edge',color='#000000') dot.attr('edge',color='#000000')
if n.ports_left == True: if n.ports_left:
loop_side = 'l' loop_side = 'l'
loop_dir = 'w' loop_dir = 'w'
elif n.ports_right == True: elif n.ports_right:
loop_side = 'r' loop_side = 'r'
loop_dir = 'e' loop_dir = 'e'
else: else:
@ -122,24 +120,23 @@ class Harness:
dot.edge('{name}:p{port_from}{loop_side}:{loop_dir}'.format(name=n.name, port_from=x[0], port_to=x[1], loop_side=loop_side, loop_dir=loop_dir), dot.edge('{name}:p{port_from}{loop_side}:{loop_dir}'.format(name=n.name, port_from=x[0], port_to=x[1], loop_side=loop_side, loop_dir=loop_dir),
'{name}:p{port_to}{loop_side}:{loop_dir}'.format(name=n.name, port_from=x[0], port_to=x[1], loop_side=loop_side, loop_dir=loop_dir)) '{name}:p{port_to}{loop_side}:{loop_dir}'.format(name=n.name, port_from=x[0], port_to=x[1], loop_side=loop_side, loop_dir=loop_dir))
for k in self.cables: for k, c in self.cables.items():
c = self.cables[k]
# a = attributes # a = attributes
a = ['{}x'.format(len(c.colors)) if c.show_num_wires == True else '', a = ['{}x'.format(len(c.colors)) if c.show_num_wires else '',
'{} mm\u00B2{}'.format(c.mm2, ' ({} AWG)'.format(awg_equiv(c.mm2)) if c.show_equiv == True else '') if c.mm2 is not None else '', '{} mm\u00B2{}'.format(c.mm2, ' ({} AWG)'.format(awg_equiv(c.mm2)) if c.show_equiv else '') if c.mm2 is not None else '',
c.awg, c.awg,
'+ S' if c.shield == True else '', '+ S' if c.shield else '',
'{} m'.format(c.length) if c.length > 0 else ''] '{} m'.format(c.length) if c.length > 0 else '']
# p = pinout # p = pinout
p = [[],[],[]] p = [[],[],[]]
for i,x in enumerate(c.colors,1): for i, x in enumerate(c.colors,1):
if c.show_pinout: if c.show_pinout:
p[0].append('<w{wireno}i>{wireno}'.format(wireno=i)) p[0].append('<w{wireno}i>{wireno}'.format(wireno=i))
p[1].append('{wirecolor}'.format(wirecolor=translate_color(x, self.color_mode))) p[1].append('{wirecolor}'.format(wirecolor=translate_color(x, self.color_mode)))
p[2].append('<w{wireno}o>{wireno}'.format(wireno=i)) p[2].append('<w{wireno}o>{wireno}'.format(wireno=i))
else: else:
p[1].append('<w{wireno}>{wirecolor}'.format(wireno=i,wirecolor=translate_color(x, self.color_mode))) p[1].append('<w{wireno}>{wirecolor}'.format(wireno=i,wirecolor=translate_color(x, self.color_mode)))
if c.shield == True: if c.shield:
if c.show_pinout: if c.show_pinout:
p[0].append('<wsi>') p[0].append('<wsi>')
p[1].append('Shield') p[1].append('Shield')
@ -147,7 +144,7 @@ class Harness:
else: else:
p[1].append('<ws>Shield') p[1].append('<ws>Shield')
# l = label # l = label
l = [c.name if c.show_name == True else '', a, p] l = [c.name if c.show_name else '', a, p]
dot.node(k, label=nested(l)) dot.node(k, label=nested(l))
# connections # connections
@ -162,10 +159,10 @@ class Harness:
dot.attr('edge',color='#000000') dot.attr('edge',color='#000000')
if x[1] is not None: # connect to left if x[1] is not None: # connect to left
dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]), dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]),
'{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='i' if c.show_pinout == True else '')) '{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='i' if c.show_pinout else ''))
# self.nodes[x[0]].ports_right = True # self.nodes[x[0]].ports_right = True
if x[4] is not None: # connect to right if x[4] is not None: # connect to right
dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='o' if c.show_pinout == True else ''), dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='o' if c.show_pinout else ''),
'{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4])) '{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4]))
# self.nodes[x[3]].ports_left = True # self.nodes[x[3]].ports_left = True

12
src/yaml2wireviz.py
View File

@ -4,7 +4,7 @@ import wireviz
filename = '../examples/ferrules.yml' filename = '../examples/ferrules.yml'
def check_designators(what, where): def check_designators(what, where):
for i,x in enumerate(what): for i, x in enumerate(what):
# print('Looking for {} in {}'.format(x,where[i])) # print('Looking for {} in {}'.format(x,where[i]))
if x not in input[where[i]]: if x not in input[where[i]]:
return False return False
@ -142,24 +142,24 @@ if 'connections' in input:
if len(from_pins) != len(to_pins): if len(from_pins) != len(to_pins):
raise Exception('List length mismatch') raise Exception('List length mismatch')
if n_w == True or w_n == True: if n_w or w_n:
for (from_pin, to_pin) in zip(from_pins, to_pins): for (from_pin, to_pin) in zip(from_pins, to_pins):
if n_w: if n_w:
h.connect(from_name, from_pin, to_name, to_pin, None, None) h.connect(from_name, from_pin, to_name, to_pin, None, None)
else: # w_n else: # w_n
h.connect(None, None, from_name, from_pin, to_name, to_pin) h.connect(None, None, from_name, from_pin, to_name, to_pin)
elif n_n == True: elif n_n:
con_name = list(con[0].keys())[0] con_name = list(con[0].keys())[0]
from_pins = expand(con[0][from_name]) from_pins = expand(con[0][from_name])
to_pins = expand(con[1][to_name]) to_pins = expand(con[1][to_name])
for (from_pin, to_pin) in zip(from_pins, to_pins): for (from_pin, to_pin) in zip(from_pins, to_pins):
h.loop(con_name, from_pin, to_pin) h.loop(con_name, from_pin, to_pin)
if f_w == True or w_f == True: if f_w or w_f:
from_pins = expand(con[0][from_name]) from_pins = expand(con[0][from_name])
to_pins = expand(con[1][to_name]) to_pins = expand(con[1][to_name])
if f_w == True: if f_w:
ferrule_name = from_name ferrule_name = from_name
wire_name = to_name wire_name = to_name
wire_pins = to_pins wire_pins = to_pins
@ -177,7 +177,7 @@ if 'connections' in input:
num_pins=ferrule.get('num_pins'), num_pins=ferrule.get('num_pins'),
pinout=ferrule.get('pinout')) pinout=ferrule.get('pinout'))
if f_w == True: if f_w:
h.connect(ferrule_id, 1, wire_name, wire_pin, None, None) h.connect(ferrule_id, 1, wire_name, wire_pin, None, None)
else: else:
h.connect(None, None, wire_name, wire_pin, ferrule_id, 1) h.connect(None, None, wire_name, wire_pin, ferrule_id, 1)