From 2dd21ae6aa90c65931e4ab31076ea70805d4dfdf Mon Sep 17 00:00:00 2001 From: Daniel Rojas Date: Fri, 29 May 2020 19:20:10 +0200 Subject: [PATCH 1/8] Change some default parameter values --- examples/example2.yml | 4 ++++ src/wireviz.py | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/examples/example2.yml b/examples/example2.yml index 54adfaf..34dbf2b 100644 --- a/examples/example2.yml +++ b/examples/example2.yml @@ -30,16 +30,20 @@ nodes: wires: W1: <<: *wire_i2c + show_name: false W2: <<: *wire_i2c + show_name: false W3: mm2: 0.14 length: 0.2 colors: [BK, BU, OG, VT] + show_name: false W4: mm2: 0.5 length: 0.35 colors: [BK, RD] + show_name: false connections: - diff --git a/src/wireviz.py b/src/wireviz.py index fa47aea..40cc50e 100644 --- a/src/wireviz.py +++ b/src/wireviz.py @@ -184,8 +184,8 @@ class Node: gender: str = None num_pins: int = None pinout: List[Any] = field(default_factory=list) - show_name: bool = False - show_num_pins: bool = False + show_name: bool = True + show_num_pins: bool = True def __post_init__(self): self.ports_left = False @@ -214,7 +214,7 @@ class Cable: shield: bool = False colors: List[Any] = field(default_factory=list) color_code: str = None - show_name: bool = False + show_name: bool = True show_pinout: bool = False show_num_wires: bool = True From df6df75a317ad0c51bdacd9e15cacfeabf073702 Mon Sep 17 00:00:00 2001 From: Daniel Rojas Date: Fri, 29 May 2020 19:20:18 +0200 Subject: [PATCH 2/8] Restructure to-do list --- todo.md | 67 +++++++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 49 insertions(+), 18 deletions(-) diff --git a/todo.md b/todo.md index f27e892..3aa98c8 100644 --- a/todo.md +++ b/todo.md @@ -1,28 +1,59 @@ # To-do: -* Set global parameters (show_pins, ...) and allow override on per-item basis +## Support for more connector types + * Generic connectors - * ferrules - * blade terminals - * loose ends - * graphical representation? -* Support for cable splicing (as connector type) -* new wire look? - * distinguish between cables and wire bundles -* improve nomenclature + * Ferrules + * Blade terminals + * Loose ends / stubs + * Graphical representation? +* Inline connectors (IDC) + * Possibly join two logical wires into one physical wire, add up length for BOM creation + * Designators like W1_1, W1_2 or similar to group them? + +## Support for more wire types + +* Coax cables + * Graphical representation +* Twisted pairs + * Logical representation + * Graphical representation +* Ribbon cables + * Folds + * Splits + * Orientation of IDC connectors + +## Support for more links/connections + +* Cable splicing + * as pseudo-connector? +* Cable bundles +* Heatshrink / sheathing + +## Visualization + +* New wire look? + * Distinguish between cables and wire bundles +* Show from/to inside wire node (better netlist) +* Display picture of connector underneath (including pin 1 location) + +## Export + +* Export to PDF with frame, title block, ... +* Automatic BOM generation + +## Other + +* Set global parameters (show_pins, ...) and allow override on per-item basis +* Improve nomenclature * terminal (connector, ferrule, blade, loose) * link (cable, wire bundle) -* show from/to inside wire node * Allow custom GraphViz code before/after WireViz-generated code -* Display picture of connector underneath (including pin 1 location) -* export to PDF with frame, title block, ... -* Automatic BOM generation -* Allow -* make "unit tests" for different features/situations - * missing parameters - * connection formats +* Make "unit tests" for different features/situations + * Missing parameters + * Connection formats * single wire 1 * multiple wires [1,2,3] * wire ranges [1-10] - * loops + * Loops * ... From 3becef78298d2a3bf15281962f61815f88137479 Mon Sep 17 00:00:00 2001 From: Daniel Rojas Date: Fri, 29 May 2020 22:37:48 +0200 Subject: [PATCH 3/8] Add support for wire bundles --- examples/bundles.yml | 65 ++++++++++++++++++++++++++++++++++++++++ examples/ferrules.yml | 6 ++-- src/wireviz.py | 69 ++++++++++++++++++++++++++++++++++++------- src/yaml2wireviz.py | 1 + 4 files changed, 126 insertions(+), 15 deletions(-) create mode 100644 examples/bundles.yml diff --git a/examples/bundles.yml b/examples/bundles.yml new file mode 100644 index 0000000..ccdf2b0 --- /dev/null +++ b/examples/bundles.yml @@ -0,0 +1,65 @@ +templates: # defining templates to be used later on + - &molex_f + type: Molex KK 254 + gender: female + - &con_i2c + pinout: [GND, +5V, SCL, SDA] + - &wire_i2c + mm2: 0.14 + length: 0.2 + colors: [BK, RD, YE, GN] + +nodes: + X1: + <<: *molex_f # copying items from the template + pinout: [GND, +5V, SCL, SDA, MISO, MOSI, SCK, N/C] + X2: + <<: *molex_f + <<: *con_i2c # it is possible to copy from more than one template + X3: + <<: *molex_f + <<: *con_i2c + X4: + <<: *molex_f + pinout: [GND, +12V, MISO, MOSI, flachstecker] + X5: + type: Molex Micro-Fit + gender: male + pinout: [GND, +12V] + +wires: + W1: + <<: *wire_i2c + type: bundle + W2: + <<: *wire_i2c + type: bundle + W3: + mm2: 0.14 + # length: 0.2 + type: bundle + colors: [BK, BU, OG, VT] + W4: + mm2: 0.5 + length: 0.35 + colors: [BK, RD] + type: bundle + show_num_wires: false + +connections: + - + - X1: [1-4] + - W1: [1-4] + - X2: [1-4] + - + - X1: [1-4] + - W2: [1-4] + - X3: [1-4] + - + - X1: [1,5-7] + - W3: [1-4] + - X4: [1,3-5] + - + - X5: [1,2] + - W4: [1,2] + - X4: [1,2] diff --git a/examples/ferrules.yml b/examples/ferrules.yml index 9fb8319..8a88f62 100644 --- a/examples/ferrules.yml +++ b/examples/ferrules.yml @@ -11,10 +11,11 @@ nodes: wires: W1: mm2: 0.25 + show_equiv: true length: 0.2 color_code: IEC num_wires: 10 - shield: true + type: bundle ferrules: F_test: @@ -25,9 +26,6 @@ connections: - X1: [1-3] - W1: [1-3] - X2: [1-3] - - - - X1: 4 - - W1: s - - F_test - W1: [4-10] diff --git a/src/wireviz.py b/src/wireviz.py index 40cc50e..f02899a 100644 --- a/src/wireviz.py +++ b/src/wireviz.py @@ -15,7 +15,7 @@ color_hex = { 'RD': '#ff0000', 'OG': '#ff8000', 'YE': '#ffff00', - 'GN': '#009900', + 'GN': '#00ff00', 'TQ': '#00ffff', 'BU': '#0066ff', 'VT': '#8000ff', @@ -79,9 +79,17 @@ class Harness: dot.body.append('// Graph generated by WireViz') dot.body.append('// https://github.com/formatc1702/WireViz') font = 'arial' - dot.attr('graph', rankdir='LR', ranksep='2', bgcolor='transparent', fontname=font) - dot.attr('node', shape='record', style='rounded,filled', fillcolor='white', fontname=font) - dot.attr('edge', style='bold', fontname=font) + dot.attr('graph', rankdir='LR', + ranksep='2', + bgcolor='transparent', + nodesep='0.33', + fontname=font) + dot.attr('node', shape='record', + style='filled', + fillcolor='white', + fontname=font) + dot.attr('edge', style='bold', + fontname=font) # prepare ports on connectors depending on which side they will connect for k, c in self.cables.items(): @@ -147,9 +155,29 @@ class Harness: p[1].append('Shield') # l = label l = [c.name if c.show_name else '', a, p] - dot.node(k, label=nested(l)) + if c.type == 'bundle': + # create subgraph for wire bundle, add to main graph afterwards + bun = Graph(name='cluster_{}'.format(k)) + labeltext = ' | '.join(p for p in a if p) + '\n ' # newline to add space between label and wires + bun.attr('graph', label=labeltext, + style='filled, dashed', + fillcolor='white') + bun.attr('node', shape='point', + label='', + fixedsize='true', + width='0', height='0') + for i, x in enumerate(c.colors,1): + bun.node('{}_w{}l'.format(k,i)) + bun.node('{}_w{}r'.format(k,i)) + else: + dot.node(k, label=nested(l)) + + # add bundle subgraph to main graph + if c.type == 'bundle': + dot.subgraph(bun) # connections + existing_connections = [] # for bundles, avoid multiple edges between a bundle's wire's start and end node for x in c.connections: if isinstance(x[2], int): # check if it's an actual wire and not a shield search_color = c.colors[x[2]-1] @@ -159,14 +187,32 @@ class Harness: dot.attr('edge',color='#000000') else: # it's a shield connection dot.attr('edge',color='#000000') + + if c.type == 'bundle': + labeltext = '{sp}{color}'.format(color=translate_color(c.colors[x[2]-1], self.color_mode), sp=' ' * 35) + if x[2] not in existing_connections: + dot.edge('{via_name}_w{via_wire}l'.format(via_name=c.name, via_wire=x[2]), + '{via_name}_w{via_wire}r'.format(via_name=c.name, via_wire=x[2]), + taillabel=labeltext, + labelangle='60', + labeldist='0', + labelfloat='true') + existing_connections.append(x[2]) + if x[1] is not None: # connect to left - dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]), - '{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='i' if c.show_pinout else '')) - # self.nodes[x[0]].ports_right = True + if c.type == 'bundle': + dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]), + '{via_name}_w{via_wire}l:w'.format(via_name=c.name, via_wire=x[2])) + else: + dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]), + '{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='i' if c.show_pinout else '')) if x[4] is not None: # connect to right - dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='o' if c.show_pinout else ''), - '{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4])) - # self.nodes[x[3]].ports_left = True + if c.type == 'bundle': + dot.edge('{via_name}_w{via_wire}r:e'.format(via_name=c.name, via_wire=x[2]), + '{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4])) + else: + dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='o' if c.show_pinout else ''), + '{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4])) return dot @@ -206,6 +252,7 @@ class Node: @dataclass class Cable: name: str + type: str = None mm2: float = None awg: int = None show_equiv: bool = False diff --git a/src/yaml2wireviz.py b/src/yaml2wireviz.py index b922d4e..2275e3c 100644 --- a/src/yaml2wireviz.py +++ b/src/yaml2wireviz.py @@ -4,6 +4,7 @@ import wireviz filename = '../examples/example1.yml' filename = '../examples/example2.yml' filename = '../examples/ferrules.yml' +filename = '../examples/bundles.yml' def check_designators(what, where): for i, x in enumerate(what): From 12b4746e018052487f3e8081885a7114b6dc4f35 Mon Sep 17 00:00:00 2001 From: Daniel Rojas Date: Fri, 29 May 2020 22:45:19 +0200 Subject: [PATCH 4/8] Fine-tune examples --- examples/bundles.yml | 2 +- examples/example2.yml | 27 +-------------------------- 2 files changed, 2 insertions(+), 27 deletions(-) diff --git a/examples/bundles.yml b/examples/bundles.yml index ccdf2b0..3e5c6c1 100644 --- a/examples/bundles.yml +++ b/examples/bundles.yml @@ -21,7 +21,7 @@ nodes: <<: *con_i2c X4: <<: *molex_f - pinout: [GND, +12V, MISO, MOSI, flachstecker] + pinout: [GND, +12V, MISO, MOSI, SCK] X5: type: Molex Micro-Fit gender: male diff --git a/examples/example2.yml b/examples/example2.yml index 34dbf2b..494c2b9 100644 --- a/examples/example2.yml +++ b/examples/example2.yml @@ -21,7 +21,7 @@ nodes: <<: *con_i2c X4: <<: *molex_f - pinout: [GND, +12V, MISO, MOSI, flachstecker] + pinout: [GND, +12V, MISO, MOSI, SCK] X5: type: Molex Micro-Fit gender: male @@ -62,28 +62,3 @@ connections: - X5: [1,2] - W4: [1,2] - X4: [1,2] - -# - -# - X1: 1 -# - W1: 1 -# - X2: 1 -# - -# - X1: [2,3,4] -# - W1: [2,3,4] -# - X2: [4,3,2] -# - -# - X1: [5-10] -# - W1: [5-7,10,9,8] -# - X2: [10-5] -# - -# - X1: 11 -# - W1: s -# - -# - X1: [1-5] -# - W1: [11-15] -# - -# - W1: [12-15] -# - X2: [2-5] -# - -# - X1: [12,14] -# - X1: [13,15] From fcf67145bf256427b980bb08166926db0f51ea08 Mon Sep 17 00:00:00 2001 From: Daniel Rojas Date: Fri, 29 May 2020 22:55:39 +0200 Subject: [PATCH 5/8] Show from/to designators on wire bundle --- examples/bundles.yml | 3 +-- src/wireviz.py | 15 ++++++++++----- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/examples/bundles.yml b/examples/bundles.yml index 3e5c6c1..052781d 100644 --- a/examples/bundles.yml +++ b/examples/bundles.yml @@ -36,7 +36,7 @@ wires: type: bundle W3: mm2: 0.14 - # length: 0.2 + length: 0.2 type: bundle colors: [BK, BU, OG, VT] W4: @@ -44,7 +44,6 @@ wires: length: 0.35 colors: [BK, RD] type: bundle - show_num_wires: false connections: - diff --git a/src/wireviz.py b/src/wireviz.py index f02899a..bb4d637 100644 --- a/src/wireviz.py +++ b/src/wireviz.py @@ -195,21 +195,26 @@ class Harness: '{via_name}_w{via_wire}r'.format(via_name=c.name, via_wire=x[2]), taillabel=labeltext, labelangle='60', - labeldist='0', - labelfloat='true') + labeldist='0') existing_connections.append(x[2]) if x[1] is not None: # connect to left if c.type == 'bundle': dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]), - '{via_name}_w{via_wire}l:w'.format(via_name=c.name, via_wire=x[2])) + '{via_name}_w{via_wire}l:w'.format(via_name=c.name, via_wire=x[2]), + headlabel='{}{}:{}'.format(' ' * 12,x[0],x[1]), + labelangle='-60', + labeldist='0') else: dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]), '{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='i' if c.show_pinout else '')) if x[4] is not None: # connect to right if c.type == 'bundle': dot.edge('{via_name}_w{via_wire}r:e'.format(via_name=c.name, via_wire=x[2]), - '{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4])) + '{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4]), + taillabel='{}:{}{}'.format(x[3],x[4],' ' * 12), + labelangle='60', + labeldist='0') else: dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='o' if c.show_pinout else ''), '{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4])) @@ -333,7 +338,7 @@ def translate_color(input, color_mode): if color_mode == 'full': output = color_full[input].lower() elif color_mode == 'FULL': - output = color_hex[input].upper() + output = color_full[input].upper() elif color_mode == 'hex': output = color_hex[input].lower() elif color_mode == 'HEX': From 9ff48eed3bf3c34cc93b07e3f104d600c9f8e735 Mon Sep 17 00:00:00 2001 From: Daniel Rojas Date: Fri, 29 May 2020 23:04:46 +0200 Subject: [PATCH 6/8] Make connection definition more readable, Pt. I --- src/wireviz.py | 43 ++++++++++++++++++++++++------------------- 1 file changed, 24 insertions(+), 19 deletions(-) diff --git a/src/wireviz.py b/src/wireviz.py index bb4d637..de57342 100644 --- a/src/wireviz.py +++ b/src/wireviz.py @@ -179,8 +179,13 @@ class Harness: # connections existing_connections = [] # for bundles, avoid multiple edges between a bundle's wire's start and end node for x in c.connections: - if isinstance(x[2], int): # check if it's an actual wire and not a shield - search_color = c.colors[x[2]-1] + from_name = x[0] + from_port = x[1] + via_port = x[2] + to_name = x[3] + to_port = x[4] + if isinstance(via_port, int): # check if it's an actual wire and not a shield + search_color = c.colors[via_port-1] if search_color in color_hex: dot.attr('edge',color='#000000:{wire_color}:#000000'.format(wire_color=color_hex[search_color])) else: # color name not found @@ -189,35 +194,35 @@ class Harness: dot.attr('edge',color='#000000') if c.type == 'bundle': - labeltext = '{sp}{color}'.format(color=translate_color(c.colors[x[2]-1], self.color_mode), sp=' ' * 35) - if x[2] not in existing_connections: - dot.edge('{via_name}_w{via_wire}l'.format(via_name=c.name, via_wire=x[2]), - '{via_name}_w{via_wire}r'.format(via_name=c.name, via_wire=x[2]), + labeltext = '{sp}{color}'.format(color=translate_color(c.colors[via_port-1], self.color_mode), sp=' ' * 35) + if via_port not in existing_connections: + dot.edge('{via_name}_w{via_wire}l'.format(via_name=c.name, via_wire=via_port), + '{via_name}_w{via_wire}r'.format(via_name=c.name, via_wire=via_port), taillabel=labeltext, labelangle='60', labeldist='0') - existing_connections.append(x[2]) + existing_connections.append(via_port) - if x[1] is not None: # connect to left + if from_port is not None: # connect to left if c.type == 'bundle': - dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]), - '{via_name}_w{via_wire}l:w'.format(via_name=c.name, via_wire=x[2]), - headlabel='{}{}:{}'.format(' ' * 12,x[0],x[1]), + dot.edge('{from_name}:p{from_port}r'.format(from_name=from_name,from_port=from_port), + '{via_name}_w{via_wire}l:w'.format(via_name=c.name, via_wire=via_port), + headlabel='{}{}:{}'.format(' ' * 12,from_name,from_port), labelangle='-60', labeldist='0') else: - dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]), - '{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='i' if c.show_pinout else '')) - if x[4] is not None: # connect to right + dot.edge('{from_name}:p{from_port}r'.format(from_name=from_name,from_port=from_port), + '{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=via_port, via_subport='i' if c.show_pinout else '')) + if to_port is not None: # connect to right if c.type == 'bundle': - dot.edge('{via_name}_w{via_wire}r:e'.format(via_name=c.name, via_wire=x[2]), - '{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4]), - taillabel='{}:{}{}'.format(x[3],x[4],' ' * 12), + dot.edge('{via_name}_w{via_wire}r:e'.format(via_name=c.name, via_wire=via_port), + '{to_name}:p{to_port}l'.format(to_name=to_name, to_port=to_port), + taillabel='{}:{}{}'.format(to_name,to_port,' ' * 12), labelangle='60', labeldist='0') else: - dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='o' if c.show_pinout else ''), - '{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4])) + dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=via_port, via_subport='o' if c.show_pinout else ''), + '{to_name}:p{to_port}l'.format(to_name=to_name, to_port=to_port)) return dot From c93fb74d177c69e7917bb2f10cc7fc17c5501b5f Mon Sep 17 00:00:00 2001 From: Daniel Rojas Date: Fri, 29 May 2020 23:18:37 +0200 Subject: [PATCH 7/8] Make connection definition more readable, Pt. II: Create connection dataclass --- src/wireviz.py | 68 ++++++++++++++++++++++++++------------------------ 1 file changed, 36 insertions(+), 32 deletions(-) diff --git a/src/wireviz.py b/src/wireviz.py index de57342..47f8dbd 100644 --- a/src/wireviz.py +++ b/src/wireviz.py @@ -94,10 +94,10 @@ class Harness: # prepare ports on connectors depending on which side they will connect for k, c in self.cables.items(): for x in c.connections: - if x[1] is not None: # connect to left - self.nodes[x[0]].ports_right = True - if x[4] is not None: # connect to right - self.nodes[x[3]].ports_left = True + if x.from_port is not None: # connect to left + self.nodes[x.from_name].ports_right = True + if x.to_port is not None: # connect to right + self.nodes[x.to_name].ports_left = True for k, n in self.nodes.items(): # a = attributes @@ -126,9 +126,9 @@ class Harness: loop_dir = 'e' else: raise Exception('No side for loops') - for x in n.loops: - dot.edge('{name}:p{port_from}{loop_side}:{loop_dir}'.format(name=n.name, port_from=x[0], port_to=x[1], loop_side=loop_side, loop_dir=loop_dir), - '{name}:p{port_to}{loop_side}:{loop_dir}'.format(name=n.name, port_from=x[0], port_to=x[1], loop_side=loop_side, loop_dir=loop_dir)) + for loop in n.loops: + dot.edge('{name}:p{port_from}{loop_side}:{loop_dir}'.format(name=n.name, port_from=loop[0], port_to=loop[1], loop_side=loop_side, loop_dir=loop_dir), + '{name}:p{port_to}{loop_side}:{loop_dir}'.format(name=n.name, port_from=loop[0], port_to=loop[1], loop_side=loop_side, loop_dir=loop_dir)) for k, c in self.cables.items(): # a = attributes @@ -179,13 +179,8 @@ class Harness: # connections existing_connections = [] # for bundles, avoid multiple edges between a bundle's wire's start and end node for x in c.connections: - from_name = x[0] - from_port = x[1] - via_port = x[2] - to_name = x[3] - to_port = x[4] - if isinstance(via_port, int): # check if it's an actual wire and not a shield - search_color = c.colors[via_port-1] + if isinstance(x.via_port, int): # check if it's an actual wire and not a shield + search_color = c.colors[x.via_port-1] if search_color in color_hex: dot.attr('edge',color='#000000:{wire_color}:#000000'.format(wire_color=color_hex[search_color])) else: # color name not found @@ -194,35 +189,35 @@ class Harness: dot.attr('edge',color='#000000') if c.type == 'bundle': - labeltext = '{sp}{color}'.format(color=translate_color(c.colors[via_port-1], self.color_mode), sp=' ' * 35) - if via_port not in existing_connections: - dot.edge('{via_name}_w{via_wire}l'.format(via_name=c.name, via_wire=via_port), - '{via_name}_w{via_wire}r'.format(via_name=c.name, via_wire=via_port), + labeltext = '{sp}{color}'.format(color=translate_color(c.colors[x.via_port-1], self.color_mode), sp=' ' * 35) + if x.via_port not in existing_connections: + dot.edge('{via_name}_w{via_wire}l'.format(via_name=c.name, via_wire=x.via_port), + '{via_name}_w{via_wire}r'.format(via_name=c.name, via_wire=x.via_port), taillabel=labeltext, labelangle='60', labeldist='0') - existing_connections.append(via_port) + existing_connections.append(x.via_port) - if from_port is not None: # connect to left + if x.from_port is not None: # connect to left if c.type == 'bundle': - dot.edge('{from_name}:p{from_port}r'.format(from_name=from_name,from_port=from_port), - '{via_name}_w{via_wire}l:w'.format(via_name=c.name, via_wire=via_port), - headlabel='{}{}:{}'.format(' ' * 12,from_name,from_port), + dot.edge('{from_name}:p{from_port}r'.format(from_name=x.from_name, from_port=x.from_port), + '{via_name}_w{via_wire}l:w'.format(via_name=c.name, via_wire=x.via_port), + headlabel='{}{}:{}'.format(' ' * 12, x.from_name, x.from_port), labelangle='-60', labeldist='0') else: - dot.edge('{from_name}:p{from_port}r'.format(from_name=from_name,from_port=from_port), - '{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=via_port, via_subport='i' if c.show_pinout else '')) - if to_port is not None: # connect to right + dot.edge('{from_name}:p{from_port}r'.format(from_name=x.from_name, from_port=x.from_port), + '{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x.via_port, via_subport='i' if c.show_pinout else '')) + if x.to_port is not None: # connect to right if c.type == 'bundle': - dot.edge('{via_name}_w{via_wire}r:e'.format(via_name=c.name, via_wire=via_port), - '{to_name}:p{to_port}l'.format(to_name=to_name, to_port=to_port), - taillabel='{}:{}{}'.format(to_name,to_port,' ' * 12), + dot.edge('{via_name}_w{via_wire}r:e'.format(via_name=c.name, via_wire=x.via_port), + '{to_name}:p{to_port}l'.format(to_name=x.to_name, to_port=x.to_port), + taillabel='{}:{}{}'.format(x.to_name, x.to_port,' ' * 12), labelangle='60', labeldist='0') else: - dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=via_port, via_subport='o' if c.show_pinout else ''), - '{to_name}:p{to_port}l'.format(to_name=to_name, to_port=to_port)) + dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x.via_port, via_subport='o' if c.show_pinout else ''), + '{to_name}:p{to_port}l'.format(to_name=x.to_name, to_port=x.to_port)) return dot @@ -309,11 +304,20 @@ class Cable: if len(from_pin) != len(to_pin): raise Exception('from_pin must have the same number of elements as to_pin') for i, x in enumerate(from_pin): - self.connections.append((from_name, from_pin[i], via_pin[i], to_name, to_pin[i])) + # self.connections.append((from_name, from_pin[i], via_pin[i], to_name, to_pin[i])) + self.connections.append(Connection(from_name, from_pin[i], via_pin[i], to_name, to_pin[i])) def connect_all_straight(self, from_name, to_name): self.connect(from_name, 'auto', 'auto', to_name, 'auto') +@dataclass +class Connection: + from_name: Any + from_port: Any + via_port: Any + to_name: Any + to_port: Any + def nested(input): l = [] for x in input: From f04441f903857147eb315e81198bd1d9929eade0 Mon Sep 17 00:00:00 2001 From: Daniel Rojas Date: Fri, 29 May 2020 23:21:54 +0200 Subject: [PATCH 8/8] Update to-do list --- src/wireviz.py | 1 - todo.md | 5 ++--- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/wireviz.py b/src/wireviz.py index 47f8dbd..63d803c 100644 --- a/src/wireviz.py +++ b/src/wireviz.py @@ -6,7 +6,6 @@ COLOR_CODES = {'DIN': ['WH','BN','GN','YE','GY','PK','BU','RD','BK','VT'], # ,'G 'IEC': ['BN','RD','OG','YE','GN','BU','VT','GY','WH','BK'], 'BW': ['BK','WH']} -# TODO: parse and render double-colored cables ('RDBU' etc) color_hex = { 'BK': '#000000', 'WH': '#ffffff', diff --git a/todo.md b/todo.md index 3aa98c8..2bb0277 100644 --- a/todo.md +++ b/todo.md @@ -27,14 +27,13 @@ * Cable splicing * as pseudo-connector? -* Cable bundles * Heatshrink / sheathing ## Visualization -* New wire look? - * Distinguish between cables and wire bundles +* Parse and render double-colored, striped cables ('RDBU' etc) * Show from/to inside wire node (better netlist) + * Implemented in wire bundles only * Display picture of connector underneath (including pin 1 location) ## Export