Add support for wire bundles
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Daniel Rojas
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df6df75a31
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65
examples/bundles.yml
Normal file
65
examples/bundles.yml
Normal file
@ -0,0 +1,65 @@
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templates: # defining templates to be used later on
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- &molex_f
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type: Molex KK 254
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gender: female
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- &con_i2c
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pinout: [GND, +5V, SCL, SDA]
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- &wire_i2c
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mm2: 0.14
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length: 0.2
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colors: [BK, RD, YE, GN]
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nodes:
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X1:
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<<: *molex_f # copying items from the template
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pinout: [GND, +5V, SCL, SDA, MISO, MOSI, SCK, N/C]
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X2:
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<<: *molex_f
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<<: *con_i2c # it is possible to copy from more than one template
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X3:
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<<: *molex_f
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<<: *con_i2c
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X4:
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<<: *molex_f
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pinout: [GND, +12V, MISO, MOSI, flachstecker]
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X5:
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type: Molex Micro-Fit
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gender: male
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pinout: [GND, +12V]
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wires:
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W1:
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<<: *wire_i2c
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type: bundle
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W2:
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<<: *wire_i2c
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type: bundle
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W3:
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mm2: 0.14
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# length: 0.2
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type: bundle
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colors: [BK, BU, OG, VT]
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W4:
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mm2: 0.5
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length: 0.35
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colors: [BK, RD]
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type: bundle
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show_num_wires: false
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connections:
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-
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- X1: [1-4]
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- W1: [1-4]
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- X2: [1-4]
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-
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- X1: [1-4]
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- W2: [1-4]
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- X3: [1-4]
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-
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- X1: [1,5-7]
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- W3: [1-4]
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- X4: [1,3-5]
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-
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- X5: [1,2]
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- W4: [1,2]
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- X4: [1,2]
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@ -11,10 +11,11 @@ nodes:
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wires:
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W1:
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mm2: 0.25
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show_equiv: true
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length: 0.2
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color_code: IEC
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num_wires: 10
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shield: true
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type: bundle
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ferrules:
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F_test:
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@ -25,9 +26,6 @@ connections:
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- X1: [1-3]
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- W1: [1-3]
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- X2: [1-3]
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-
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- X1: 4
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- W1: s
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-
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- F_test
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- W1: [4-10]
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@ -15,7 +15,7 @@ color_hex = {
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'RD': '#ff0000',
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'OG': '#ff8000',
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'YE': '#ffff00',
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'GN': '#009900',
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'GN': '#00ff00',
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'TQ': '#00ffff',
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'BU': '#0066ff',
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'VT': '#8000ff',
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@ -79,9 +79,17 @@ class Harness:
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dot.body.append('// Graph generated by WireViz')
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dot.body.append('// https://github.com/formatc1702/WireViz')
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font = 'arial'
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dot.attr('graph', rankdir='LR', ranksep='2', bgcolor='transparent', fontname=font)
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dot.attr('node', shape='record', style='rounded,filled', fillcolor='white', fontname=font)
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dot.attr('edge', style='bold', fontname=font)
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dot.attr('graph', rankdir='LR',
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ranksep='2',
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bgcolor='transparent',
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nodesep='0.33',
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fontname=font)
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dot.attr('node', shape='record',
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style='filled',
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fillcolor='white',
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fontname=font)
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dot.attr('edge', style='bold',
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fontname=font)
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# prepare ports on connectors depending on which side they will connect
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for k, c in self.cables.items():
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@ -147,9 +155,29 @@ class Harness:
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p[1].append('<ws>Shield')
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# l = label
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l = [c.name if c.show_name else '', a, p]
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dot.node(k, label=nested(l))
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if c.type == 'bundle':
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# create subgraph for wire bundle, add to main graph afterwards
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bun = Graph(name='cluster_{}'.format(k))
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labeltext = ' | '.join(p for p in a if p) + '\n ' # newline to add space between label and wires
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bun.attr('graph', label=labeltext,
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style='filled, dashed',
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fillcolor='white')
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bun.attr('node', shape='point',
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label='',
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fixedsize='true',
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width='0', height='0')
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for i, x in enumerate(c.colors,1):
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bun.node('{}_w{}l'.format(k,i))
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bun.node('{}_w{}r'.format(k,i))
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else:
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dot.node(k, label=nested(l))
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# add bundle subgraph to main graph
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if c.type == 'bundle':
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dot.subgraph(bun)
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# connections
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existing_connections = [] # for bundles, avoid multiple edges between a bundle's wire's start and end node
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for x in c.connections:
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if isinstance(x[2], int): # check if it's an actual wire and not a shield
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search_color = c.colors[x[2]-1]
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@ -159,14 +187,32 @@ class Harness:
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dot.attr('edge',color='#000000')
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else: # it's a shield connection
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dot.attr('edge',color='#000000')
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if c.type == 'bundle':
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labeltext = '{sp}{color}'.format(color=translate_color(c.colors[x[2]-1], self.color_mode), sp=' ' * 35)
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if x[2] not in existing_connections:
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dot.edge('{via_name}_w{via_wire}l'.format(via_name=c.name, via_wire=x[2]),
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'{via_name}_w{via_wire}r'.format(via_name=c.name, via_wire=x[2]),
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taillabel=labeltext,
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labelangle='60',
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labeldist='0',
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labelfloat='true')
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existing_connections.append(x[2])
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if x[1] is not None: # connect to left
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dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]),
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'{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='i' if c.show_pinout else ''))
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# self.nodes[x[0]].ports_right = True
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if c.type == 'bundle':
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dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]),
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'{via_name}_w{via_wire}l:w'.format(via_name=c.name, via_wire=x[2]))
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else:
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dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]),
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'{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='i' if c.show_pinout else ''))
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if x[4] is not None: # connect to right
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dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='o' if c.show_pinout else ''),
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'{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4]))
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# self.nodes[x[3]].ports_left = True
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if c.type == 'bundle':
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dot.edge('{via_name}_w{via_wire}r:e'.format(via_name=c.name, via_wire=x[2]),
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'{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4]))
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else:
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dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='o' if c.show_pinout else ''),
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'{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4]))
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return dot
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@ -206,6 +252,7 @@ class Node:
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@dataclass
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class Cable:
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name: str
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type: str = None
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mm2: float = None
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awg: int = None
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show_equiv: bool = False
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@ -4,6 +4,7 @@ import wireviz
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filename = '../examples/example1.yml'
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filename = '../examples/example2.yml'
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filename = '../examples/ferrules.yml'
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filename = '../examples/bundles.yml'
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def check_designators(what, where):
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for i, x in enumerate(what):
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