diff --git a/examples/demo01.gv b/examples/demo01.gv new file mode 100644 index 0000000..c23e536 --- /dev/null +++ b/examples/demo01.gv @@ -0,0 +1,23 @@ +graph { +// Graph generated by WireViz +// https://github.com/formatc1702/WireViz + graph [bgcolor=transparent fontname=arial nodesep=0.33 rankdir=LR ranksep=2] + node [fillcolor=white fontname=arial shape=record style=filled] + edge [fontname=arial style=bold] + X1 [label="X1|{D-Sub|female|9-pin}|{{DCD|RX|TX|DTR|GND|DSR|RTS|CTS|RI}|{1|2|3|4|5|6|7|8|9}}"] + X2 [label="X2|{Molex KK 254|female|6-pin}|{{1|2|3|4|5|6}|{GND|RX|TX|N/C|OUT|IN}}"] + edge [color="#000000"] + X2:p5l:w -- X2:p6l:w + W1 [label="W1|{3x|0.25 mm²|+ S|0.2 m}|{{WH|BN|GN|Shield}}"] + edge [color="#000000:#ffffff:#000000"] + X1:p5r -- W1:w1 + W1:w1 -- X2:p1l + edge [color="#000000:#666600:#000000"] + X1:p2r -- W1:w2 + W1:w2 -- X2:p3l + edge [color="#000000:#00ff00:#000000"] + X1:p1r -- W1:w3 + W1:w3 -- X2:p2l + edge [color="#000000"] + X1:p5r -- W1:ws +} diff --git a/examples/demo01.png b/examples/demo01.png new file mode 100644 index 0000000..2d74b55 Binary files /dev/null and b/examples/demo01.png differ diff --git a/examples/demo01.svg b/examples/demo01.svg new file mode 100644 index 0000000..7615ca0 --- /dev/null +++ b/examples/demo01.svg @@ -0,0 +1,169 @@ + + + + + + + + +X1 + +X1 + +D-Sub + +female + +9-pin + +DCD + +RX + +TX + +DTR + +GND + +DSR + +RTS + +CTS + +RI + +1 + +2 + +3 + +4 + +5 + +6 + +7 + +8 + +9 + + + +W1 + +W1 + +3x + +0.25 mm² + ++ S + +0.2 m + +WH + +BN + +GN + +Shield + + + +X1:p5r--W1:w1 + + + + + + +X1:p2r--W1:w2 + + + + + + +X1:p1r--W1:w3 + + + + + + +X1:p5r--W1:ws + + + + +X2 + +X2 + +Molex KK 254 + +female + +6-pin + +1 + +2 + +3 + +4 + +5 + +6 + +GND + +RX + +TX + +N/C + +OUT + +IN + + + +X2:w--X2:w + + + + +W1:w1--X2:p1l + + + + + + +W1:w2--X2:p3l + + + + + + +W1:w3--X2:p2l + + + + + + diff --git a/examples/example1.yml b/examples/demo01.yml similarity index 100% rename from examples/example1.yml rename to examples/demo01.yml diff --git a/examples/demo02.gv b/examples/demo02.gv new file mode 100644 index 0000000..5dbe6b5 --- /dev/null +++ b/examples/demo02.gv @@ -0,0 +1,116 @@ +graph { +// Graph generated by WireViz +// https://github.com/formatc1702/WireViz + graph [bgcolor=transparent fontname=arial nodesep=0.33 rankdir=LR ranksep=2] + node [fillcolor=white fontname=arial shape=record style=filled] + edge [fontname=arial style=bold] + X1 [label="X1|{Molex KK 254|female|8-pin}|{{GND|+5V|SCL|SDA|MISO|MOSI|SCK|N/C}|{1|2|3|4|5|6|7|8}}"] + X2 [label="X2|{Molex KK 254|female|4-pin}|{{1|2|3|4}|{GND|+5V|SCL|SDA}}"] + X3 [label="X3|{Molex KK 254|female|4-pin}|{{1|2|3|4}|{GND|+5V|SCL|SDA}}"] + X4 [label="X4|{Molex KK 254|female|5-pin}|{{1|2|3|4|5}|{GND|+12V|MISO|MOSI|SCK}}"] + X5 [label="X5|{Molex Micro-Fit|male|2-pin}|{{GND|+12V}|{1|2}}"] + subgraph cluster_W1 { + graph [fillcolor=white label="4x | 0.14 mm² (26 AWG) | 0.2 m + " style="filled, dashed"] + node [fixedsize=true height=0 label="" shape=point width=0] + W1_w1l + W1_w1r + W1_w2l + W1_w2r + W1_w3l + W1_w3r + W1_w4l + W1_w4r + } + edge [color="#000000:#000000:#000000"] + W1_w1l -- W1_w1r [labelangle=60 labeldist=0 taillabel=" BK"] + X1:p1r -- W1_w1l:w [headlabel=" X1:1" labelangle=-60 labeldist=0] + W1_w1r:e -- X2:p1l [labelangle=60 labeldist=0 taillabel="X2:1 "] + edge [color="#000000:#ff0000:#000000"] + W1_w2l -- W1_w2r [labelangle=60 labeldist=0 taillabel=" RD"] + X1:p2r -- W1_w2l:w [headlabel=" X1:2" labelangle=-60 labeldist=0] + W1_w2r:e -- X2:p2l [labelangle=60 labeldist=0 taillabel="X2:2 "] + edge [color="#000000:#ffff00:#000000"] + W1_w3l -- W1_w3r [labelangle=60 labeldist=0 taillabel=" YE"] + X1:p3r -- W1_w3l:w [headlabel=" X1:3" labelangle=-60 labeldist=0] + W1_w3r:e -- X2:p3l [labelangle=60 labeldist=0 taillabel="X2:3 "] + edge [color="#000000:#00ff00:#000000"] + W1_w4l -- W1_w4r [labelangle=60 labeldist=0 taillabel=" GN"] + X1:p4r -- W1_w4l:w [headlabel=" X1:4" labelangle=-60 labeldist=0] + W1_w4r:e -- X2:p4l [labelangle=60 labeldist=0 taillabel="X2:4 "] + subgraph cluster_W2 { + graph [fillcolor=white label="4x | 0.14 mm² (26 AWG) | 0.2 m + " style="filled, dashed"] + node [fixedsize=true height=0 label="" shape=point width=0] + W2_w1l + W2_w1r + W2_w2l + W2_w2r + W2_w3l + W2_w3r + W2_w4l + W2_w4r + } + edge [color="#000000:#000000:#000000"] + W2_w1l -- W2_w1r [labelangle=60 labeldist=0 taillabel=" BK"] + X1:p1r -- W2_w1l:w [headlabel=" X1:1" labelangle=-60 labeldist=0] + W2_w1r:e -- X3:p1l [labelangle=60 labeldist=0 taillabel="X3:1 "] + edge [color="#000000:#ff0000:#000000"] + W2_w2l -- W2_w2r [labelangle=60 labeldist=0 taillabel=" RD"] + X1:p2r -- W2_w2l:w [headlabel=" X1:2" labelangle=-60 labeldist=0] + W2_w2r:e -- X3:p2l [labelangle=60 labeldist=0 taillabel="X3:2 "] + edge [color="#000000:#ffff00:#000000"] + W2_w3l -- W2_w3r [labelangle=60 labeldist=0 taillabel=" YE"] + X1:p3r -- W2_w3l:w [headlabel=" X1:3" labelangle=-60 labeldist=0] + W2_w3r:e -- X3:p3l [labelangle=60 labeldist=0 taillabel="X3:3 "] + edge [color="#000000:#00ff00:#000000"] + W2_w4l -- W2_w4r [labelangle=60 labeldist=0 taillabel=" GN"] + X1:p4r -- W2_w4l:w [headlabel=" X1:4" labelangle=-60 labeldist=0] + W2_w4r:e -- X3:p4l [labelangle=60 labeldist=0 taillabel="X3:4 "] + subgraph cluster_W3 { + graph [fillcolor=white label="4x | 0.14 mm² (26 AWG) | 0.2 m + " style="filled, dashed"] + node [fixedsize=true height=0 label="" shape=point width=0] + W3_w1l + W3_w1r + W3_w2l + W3_w2r + W3_w3l + W3_w3r + W3_w4l + W3_w4r + } + edge [color="#000000:#000000:#000000"] + W3_w1l -- W3_w1r [labelangle=60 labeldist=0 taillabel=" BK"] + X1:p1r -- W3_w1l:w [headlabel=" X1:1" labelangle=-60 labeldist=0] + W3_w1r:e -- X4:p1l [labelangle=60 labeldist=0 taillabel="X4:1 "] + edge [color="#000000:#0066ff:#000000"] + W3_w2l -- W3_w2r [labelangle=60 labeldist=0 taillabel=" BU"] + X1:p5r -- W3_w2l:w [headlabel=" X1:5" labelangle=-60 labeldist=0] + W3_w2r:e -- X4:p3l [labelangle=60 labeldist=0 taillabel="X4:3 "] + edge [color="#000000:#ff8000:#000000"] + W3_w3l -- W3_w3r [labelangle=60 labeldist=0 taillabel=" OG"] + X1:p6r -- W3_w3l:w [headlabel=" X1:6" labelangle=-60 labeldist=0] + W3_w3r:e -- X4:p4l [labelangle=60 labeldist=0 taillabel="X4:4 "] + edge [color="#000000:#8000ff:#000000"] + W3_w4l -- W3_w4r [labelangle=60 labeldist=0 taillabel=" VT"] + X1:p7r -- W3_w4l:w [headlabel=" X1:7" labelangle=-60 labeldist=0] + W3_w4r:e -- X4:p5l [labelangle=60 labeldist=0 taillabel="X4:5 "] + subgraph cluster_W4 { + graph [fillcolor=white label="2x | 0.5 mm² (21 AWG) | 0.35 m + " style="filled, dashed"] + node [fixedsize=true height=0 label="" shape=point width=0] + W4_w1l + W4_w1r + W4_w2l + W4_w2r + } + edge [color="#000000:#000000:#000000"] + W4_w1l -- W4_w1r [labelangle=60 labeldist=0 taillabel=" BK"] + X5:p1r -- W4_w1l:w [headlabel=" X5:1" labelangle=-60 labeldist=0] + W4_w1r:e -- X4:p1l [labelangle=60 labeldist=0 taillabel="X4:1 "] + edge [color="#000000:#ff0000:#000000"] + W4_w2l -- W4_w2r [labelangle=60 labeldist=0 taillabel=" RD"] + X5:p2r -- W4_w2l:w [headlabel=" X5:2" labelangle=-60 labeldist=0] + W4_w2r:e -- X4:p2l [labelangle=60 labeldist=0 taillabel="X4:2 "] +} diff --git a/examples/demo02.png b/examples/demo02.png new file mode 100644 index 0000000..0572b16 Binary files /dev/null and b/examples/demo02.png differ diff --git a/examples/demo02.svg b/examples/demo02.svg new file mode 100644 index 0000000..7f2532c --- /dev/null +++ b/examples/demo02.svg @@ -0,0 +1,663 @@ + + + + + + + +cluster_W1 + +4x  |  0.14 mm² (26 AWG)  |  0.2 m + + + +cluster_W2 + +4x  |  0.14 mm² (26 AWG)  |  0.2 m + + + +cluster_W3 + +4x  |  0.14 mm² (26 AWG)  |  0.2 m + + + +cluster_W4 + +2x  |  0.5 mm² (21 AWG)  |  0.35 m + + + + +X1 + +X1 + +Molex KK 254 + +female + +8-pin + +GND + ++5V + +SCL + +SDA + +MISO + +MOSI + +SCK + +N/C + +1 + +2 + +3 + +4 + +5 + +6 + +7 + +8 + + + +W1_w1l + + + + +X1:p1r--W1_w1l:w + + + +            X1:1 + + + +W1_w2l + + + + +X1:p2r--W1_w2l:w + + + +            X1:2 + + + +W1_w3l + + + + +X1:p3r--W1_w3l:w + + + +            X1:3 + + + +W1_w4l + + + + +X1:p4r--W1_w4l:w + + + +            X1:4 + + + +W2_w1l + + + + +X1:p1r--W2_w1l:w + + + +            X1:1 + + + +W2_w2l + + + + +X1:p2r--W2_w2l:w + + + +            X1:2 + + + +W2_w3l + + + + +X1:p3r--W2_w3l:w + + + +            X1:3 + + + +W2_w4l + + + + +X1:p4r--W2_w4l:w + + + +            X1:4 + + + +W3_w1l + + + + +X1:p1r--W3_w1l:w + + + +            X1:1 + + + +W3_w2l + + + + +X1:p5r--W3_w2l:w + + + +            X1:5 + + + +W3_w3l + + + + +X1:p6r--W3_w3l:w + + + +            X1:6 + + + +W3_w4l + + + + +X1:p7r--W3_w4l:w + + + +            X1:7 + + + +X2 + +X2 + +Molex KK 254 + +female + +4-pin + +1 + +2 + +3 + +4 + +GND + ++5V + +SCL + +SDA + + + +X3 + +X3 + +Molex KK 254 + +female + +4-pin + +1 + +2 + +3 + +4 + +GND + ++5V + +SCL + +SDA + + + +X4 + +X4 + +Molex KK 254 + +female + +5-pin + +1 + +2 + +3 + +4 + +5 + +GND + ++12V + +MISO + +MOSI + +SCK + + + +X5 + +X5 + +Molex Micro-Fit + +male + +2-pin + +GND + ++12V + +1 + +2 + + + +W4_w1l + + + + +X5:p1r--W4_w1l:w + + + +            X5:1 + + + +W4_w2l + + + + +X5:p2r--W4_w2l:w + + + +            X5:2 + + + +W1_w1r + + + + +W1_w1l--W1_w1r + + + +                                   BK + + + +W1_w1r:e--X2:p1l + + + +X2:1             + + + +W1_w2r + + + + +W1_w2l--W1_w2r + + + +                                   RD + + + +W1_w2r:e--X2:p2l + + + +X2:2             + + + +W1_w3r + + + + +W1_w3l--W1_w3r + + + +                                   YE + + + +W1_w3r:e--X2:p3l + + + +X2:3             + + + +W1_w4r + + + + +W1_w4l--W1_w4r + + + +                                   GN + + + +W1_w4r:e--X2:p4l + + + +X2:4             + + + +W2_w1r + + + + +W2_w1l--W2_w1r + + + +                                   BK + + + +W2_w1r:e--X3:p1l + + + +X3:1             + + + +W2_w2r + + + + +W2_w2l--W2_w2r + + + +                                   RD + + + +W2_w2r:e--X3:p2l + + + +X3:2             + + + +W2_w3r + + + + +W2_w3l--W2_w3r + + + +                                   YE + + + +W2_w3r:e--X3:p3l + + + +X3:3             + + + +W2_w4r + + + + +W2_w4l--W2_w4r + + + +                                   GN + + + +W2_w4r:e--X3:p4l + + + +X3:4             + + + +W3_w1r + + + + +W3_w1l--W3_w1r + + + +                                   BK + + + +W3_w1r:e--X4:p1l + + + +X4:1             + + + +W3_w2r + + + + +W3_w2l--W3_w2r + + + +                                   BU + + + +W3_w2r:e--X4:p3l + + + +X4:3             + + + +W3_w3r + + + + +W3_w3l--W3_w3r + + + +                                   OG + + + +W3_w3r:e--X4:p4l + + + +X4:4             + + + +W3_w4r + + + + +W3_w4l--W3_w4r + + + +                                   VT + + + +W3_w4r:e--X4:p5l + + + +X4:5             + + + +W4_w1r + + + + +W4_w1l--W4_w1r + + + +                                   BK + + + +W4_w1r:e--X4:p1l + + + +X4:1             + + + +W4_w2r + + + + +W4_w2l--W4_w2r + + + +                                   RD + + + +W4_w2r:e--X4:p2l + + + +X4:2             + + + diff --git a/examples/bundles.yml b/examples/demo02.yml similarity index 92% rename from examples/bundles.yml rename to examples/demo02.yml index 052781d..a486b37 100644 --- a/examples/bundles.yml +++ b/examples/demo02.yml @@ -31,19 +31,23 @@ wires: W1: <<: *wire_i2c type: bundle + show_equiv: true W2: <<: *wire_i2c type: bundle + show_equiv: true W3: mm2: 0.14 length: 0.2 - type: bundle colors: [BK, BU, OG, VT] + type: bundle + show_equiv: true W4: mm2: 0.5 length: 0.35 colors: [BK, RD] type: bundle + show_equiv: true connections: - diff --git a/examples/ex01.gv b/examples/ex01.gv new file mode 100644 index 0000000..4010c31 --- /dev/null +++ b/examples/ex01.gv @@ -0,0 +1,24 @@ +graph { +// Graph generated by WireViz +// https://github.com/formatc1702/WireViz + graph [bgcolor=transparent fontname=arial nodesep=0.33 rankdir=LR ranksep=2] + node [fillcolor=white fontname=arial shape=record style=filled] + edge [fontname=arial style=bold] + X1 [label="X1|{Molex KK 254|female|4-pin}|{{GND|VCC|RX|TX}|{1|2|3|4}}"] + X2 [label="X2|{Molex KK 254|female|4-pin}|{{1|2|3|4}|{GND|VCC|RX|TX}}"] + W1 [label="W1|{4x|0.25 mm² (24 AWG)|+ S|0.2 m}|{{BN|RD|OG|YE|Shield}}"] + edge [color="#000000:#666600:#000000"] + X1:p1r -- W1:w1 + W1:w1 -- X2:p1l + edge [color="#000000:#ff0000:#000000"] + X1:p2r -- W1:w2 + W1:w2 -- X2:p2l + edge [color="#000000:#ff8000:#000000"] + X1:p3r -- W1:w3 + W1:w3 -- X2:p4l + edge [color="#000000:#ffff00:#000000"] + X1:p4r -- W1:w4 + W1:w4 -- X2:p3l + edge [color="#000000"] + X1:p1r -- W1:ws +} diff --git a/examples/ex01.png b/examples/ex01.png new file mode 100644 index 0000000..f5b828e Binary files /dev/null and b/examples/ex01.png differ diff --git a/examples/ex01.svg b/examples/ex01.svg new file mode 100644 index 0000000..0a90308 --- /dev/null +++ b/examples/ex01.svg @@ -0,0 +1,152 @@ + + + + + + + + +X1 + +X1 + +Molex KK 254 + +female + +4-pin + +GND + +VCC + +RX + +TX + +1 + +2 + +3 + +4 + + + +W1 + +W1 + +4x + +0.25 mm² (24 AWG) + ++ S + +0.2 m + +BN + +RD + +OG + +YE + +Shield + + + +X1:p1r--W1:w1 + + + + + + +X1:p2r--W1:w2 + + + + + + +X1:p3r--W1:w3 + + + + + + +X1:p4r--W1:w4 + + + + + + +X1:p1r--W1:ws + + + + +X2 + +X2 + +Molex KK 254 + +female + +4-pin + +1 + +2 + +3 + +4 + +GND + +VCC + +RX + +TX + + + +W1:w1--X2:p1l + + + + + + +W1:w2--X2:p2l + + + + + + +W1:w3--X2:p4l + + + + + + +W1:w4--X2:p3l + + + + + + diff --git a/examples/ex01.yml b/examples/ex01.yml new file mode 100644 index 0000000..120c3b6 --- /dev/null +++ b/examples/ex01.yml @@ -0,0 +1,27 @@ +nodes: + X1: + type: Molex KK 254 # more information + gender: female + pinout: [GND, VCC, RX, TX] # num_pins is implicit in pinout + X2: + type: Molex KK 254 + gender: female + pinout: [GND, VCC, RX, TX] + +wires: + W1: + color_code: IEC # auto-color wires based on a standard + num_wires: 4 # need to specify number of wires explicitly when using a color code + mm2: 0.25 # metric gauge, in mm^2 + show_equiv: true # auto-calculate AWG equivalent from metric gauge + length: 0.2 # length in m + shield: true + +connections: + - + - X1: [1-4] + - W1: [1-4] + - X2: [1,2,4,3] # crossover + - # connection from connector pin to wire shielding + - X1: 1 + - W1: s diff --git a/examples/ex02.gv b/examples/ex02.gv new file mode 100644 index 0000000..7ba74d2 --- /dev/null +++ b/examples/ex02.gv @@ -0,0 +1,32 @@ +graph { +// Graph generated by WireViz +// https://github.com/formatc1702/WireViz + graph [bgcolor=transparent fontname=arial nodesep=0.33 rankdir=LR ranksep=2] + node [fillcolor=white fontname=arial shape=record style=filled] + edge [fontname=arial style=bold] + X1 [label="X1|{Molex Micro-Fit|male|2-pin}|{{GND|VCC}|{1|2}}"] + X2 [label="X2|{Molex Micro-Fit|female|2-pin}|{{1|2}|{GND|VCC}}"] + X3 [label="X3|{Molex Micro-Fit|female|2-pin}|{{1|2}|{GND|VCC}}"] + X4 [label="X4|{Molex Micro-Fit|female|2-pin}|{{1|2}|{GND|VCC}}"] + W1 [label="W1|{2x|0.25 mm² (24 AWG)|0.2 m}|{{BK|RD}}"] + edge [color="#000000:#000000:#000000"] + X1:p1r -- W1:w1 + W1:w1 -- X2:p1l + edge [color="#000000:#ff0000:#000000"] + X1:p2r -- W1:w2 + W1:w2 -- X2:p2l + W2 [label="W2|{2x|0.25 mm² (24 AWG)|0.2 m}|{{BK|RD}}"] + edge [color="#000000:#000000:#000000"] + X1:p1r -- W2:w1 + W2:w1 -- X3:p1l + edge [color="#000000:#ff0000:#000000"] + X1:p2r -- W2:w2 + W2:w2 -- X3:p2l + W3 [label="W3|{2x|0.25 mm² (24 AWG)|0.2 m}|{{BK|RD}}"] + edge [color="#000000:#000000:#000000"] + X1:p1r -- W3:w1 + W3:w1 -- X4:p1l + edge [color="#000000:#ff0000:#000000"] + X1:p2r -- W3:w2 + W3:w2 -- X4:p2l +} diff --git a/examples/ex02.png b/examples/ex02.png new file mode 100644 index 0000000..a617ee4 Binary files /dev/null and b/examples/ex02.png differ diff --git a/examples/ex02.svg b/examples/ex02.svg new file mode 100644 index 0000000..6e335d2 --- /dev/null +++ b/examples/ex02.svg @@ -0,0 +1,223 @@ + + + + + + + + +X1 + +X1 + +Molex Micro-Fit + +male + +2-pin + +GND + +VCC + +1 + +2 + + + +W1 + +W1 + +2x + +0.25 mm² (24 AWG) + +0.2 m + +BK + +RD + + + +X1:p1r--W1:w1 + + + + + + +X1:p2r--W1:w2 + + + + + + +W2 + +W2 + +2x + +0.25 mm² (24 AWG) + +0.2 m + +BK + +RD + + + +X1:p1r--W2:w1 + + + + + + +X1:p2r--W2:w2 + + + + + + +W3 + +W3 + +2x + +0.25 mm² (24 AWG) + +0.2 m + +BK + +RD + + + +X1:p1r--W3:w1 + + + + + + +X1:p2r--W3:w2 + + + + + + +X2 + +X2 + +Molex Micro-Fit + +female + +2-pin + +1 + +2 + +GND + +VCC + + + +X3 + +X3 + +Molex Micro-Fit + +female + +2-pin + +1 + +2 + +GND + +VCC + + + +X4 + +X4 + +Molex Micro-Fit + +female + +2-pin + +1 + +2 + +GND + +VCC + + + +W1:w1--X2:p1l + + + + + + +W1:w2--X2:p2l + + + + + + +W2:w1--X3:p1l + + + + + + +W2:w2--X3:p2l + + + + + + +W3:w1--X4:p1l + + + + + + +W3:w2--X4:p2l + + + + + + diff --git a/examples/ex02.yml b/examples/ex02.yml new file mode 100644 index 0000000..b990aa1 --- /dev/null +++ b/examples/ex02.yml @@ -0,0 +1,38 @@ +nodes: + X1: &boo + type: Molex Micro-Fit + gender: male + pinout: [GND, VCC] + X2: &con_power_f # define template + type: Molex Micro-Fit + gender: female + pinout: [GND, VCC] + X3: + <<: *con_power_f # create from template + X4: + <<: *con_power_f # create from template + +wires: + W1: &wire_power # define template + colors: [BK, RD] # number of wires implicit in color list + mm2: 0.25 + show_equiv: true + length: 0.2 + W2: + <<: *wire_power # create from template + W3: + <<: *wire_power # create from template + +connections: + - + - X1: [1-2] + - W1: [1-2] + - X2: [1-2] + - + - X1: [1-2] + - W2: [1-2] + - X3: [1-2] + - + - X1: [1-2] + - W3: [1-2] + - X4: [1-2] diff --git a/examples/ex03.gv b/examples/ex03.gv new file mode 100644 index 0000000..810d334 --- /dev/null +++ b/examples/ex03.gv @@ -0,0 +1,52 @@ +graph { +// Graph generated by WireViz +// https://github.com/formatc1702/WireViz + graph [bgcolor=transparent fontname=arial nodesep=0.33 rankdir=LR ranksep=2] + node [fillcolor=white fontname=arial shape=record style=filled] + edge [fontname=arial style=bold] + X1 [label="X1|{Molex Micro-Fit|male|2-pin}|{{GND|VCC}|{1|2}}"] + X2 [label="X2|{Molex Micro-Fit|female|2-pin}|{{1|2}|{GND|VCC}}"] + X3 [label="X3|{Molex Micro-Fit|female|2-pin}|{{1|2}|{GND|VCC}}"] + X4 [label="X4|{Molex Micro-Fit|female|2-pin}|{{1|2}|{GND|VCC}}"] + subgraph cluster_W1 { + graph [fillcolor=white label="6x | 0.25 mm² (24 AWG) | 0.2 m + " style="filled, dashed"] + node [fixedsize=true height=0 label="" shape=point width=0] + W1_w1l + W1_w1r + W1_w2l + W1_w2r + W1_w3l + W1_w3r + W1_w4l + W1_w4r + W1_w5l + W1_w5r + W1_w6l + W1_w6r + } + edge [color="#000000:#000000:#000000"] + W1_w1l -- W1_w1r [labelangle=60 labeldist=0 taillabel=" BK"] + X1:p1r -- W1_w1l:w [headlabel=" X1:1" labelangle=-60 labeldist=0] + W1_w1r:e -- X2:p1l [labelangle=60 labeldist=0 taillabel="X2:1 "] + edge [color="#000000:#ff0000:#000000"] + W1_w2l -- W1_w2r [labelangle=60 labeldist=0 taillabel=" RD"] + X1:p2r -- W1_w2l:w [headlabel=" X1:2" labelangle=-60 labeldist=0] + W1_w2r:e -- X2:p2l [labelangle=60 labeldist=0 taillabel="X2:2 "] + edge [color="#000000:#000000:#000000"] + W1_w3l -- W1_w3r [labelangle=60 labeldist=0 taillabel=" BK"] + X1:p1r -- W1_w3l:w [headlabel=" X1:1" labelangle=-60 labeldist=0] + W1_w3r:e -- X3:p1l [labelangle=60 labeldist=0 taillabel="X3:1 "] + edge [color="#000000:#ff0000:#000000"] + W1_w4l -- W1_w4r [labelangle=60 labeldist=0 taillabel=" RD"] + X1:p2r -- W1_w4l:w [headlabel=" X1:2" labelangle=-60 labeldist=0] + W1_w4r:e -- X3:p2l [labelangle=60 labeldist=0 taillabel="X3:2 "] + edge [color="#000000:#000000:#000000"] + W1_w5l -- W1_w5r [labelangle=60 labeldist=0 taillabel=" BK"] + X1:p1r -- W1_w5l:w [headlabel=" X1:1" labelangle=-60 labeldist=0] + W1_w5r:e -- X4:p1l [labelangle=60 labeldist=0 taillabel="X4:1 "] + edge [color="#000000:#ff0000:#000000"] + W1_w6l -- W1_w6r [labelangle=60 labeldist=0 taillabel=" RD"] + X1:p2r -- W1_w6l:w [headlabel=" X1:2" labelangle=-60 labeldist=0] + W1_w6r:e -- X4:p2l [labelangle=60 labeldist=0 taillabel="X4:2 "] +} diff --git a/examples/ex03.png b/examples/ex03.png new file mode 100644 index 0000000..f1a5e9f Binary files /dev/null and b/examples/ex03.png differ diff --git a/examples/ex03.svg b/examples/ex03.svg new file mode 100644 index 0000000..ed8a261 --- /dev/null +++ b/examples/ex03.svg @@ -0,0 +1,301 @@ + + + + + + + +cluster_W1 + +6x  |  0.25 mm² (24 AWG)  |  0.2 m + + + + +X1 + +X1 + +Molex Micro-Fit + +male + +2-pin + +GND + +VCC + +1 + +2 + + + +W1_w1l + + + + +X1:p1r--W1_w1l:w + + + +            X1:1 + + + +W1_w2l + + + + +X1:p2r--W1_w2l:w + + + +            X1:2 + + + +W1_w3l + + + + +X1:p1r--W1_w3l:w + + + +            X1:1 + + + +W1_w4l + + + + +X1:p2r--W1_w4l:w + + + +            X1:2 + + + +W1_w5l + + + + +X1:p1r--W1_w5l:w + + + +            X1:1 + + + +W1_w6l + + + + +X1:p2r--W1_w6l:w + + + +            X1:2 + + + +X2 + +X2 + +Molex Micro-Fit + +female + +2-pin + +1 + +2 + +GND + +VCC + + + +X3 + +X3 + +Molex Micro-Fit + +female + +2-pin + +1 + +2 + +GND + +VCC + + + +X4 + +X4 + +Molex Micro-Fit + +female + +2-pin + +1 + +2 + +GND + +VCC + + + +W1_w1r + + + + +W1_w1l--W1_w1r + + + +                                   BK + + + +W1_w1r:e--X2:p1l + + + +X2:1             + + + +W1_w2r + + + + +W1_w2l--W1_w2r + + + +                                   RD + + + +W1_w2r:e--X2:p2l + + + +X2:2             + + + +W1_w3r + + + + +W1_w3l--W1_w3r + + + +                                   BK + + + +W1_w3r:e--X3:p1l + + + +X3:1             + + + +W1_w4r + + + + +W1_w4l--W1_w4r + + + +                                   RD + + + +W1_w4r:e--X3:p2l + + + +X3:2             + + + +W1_w5r + + + + +W1_w5l--W1_w5r + + + +                                   BK + + + +W1_w5r:e--X4:p1l + + + +X4:1             + + + +W1_w6r + + + + +W1_w6l--W1_w6r + + + +                                   RD + + + +W1_w6r:e--X4:p2l + + + +X4:2             + + + diff --git a/examples/ex03.yml b/examples/ex03.yml new file mode 100644 index 0000000..c28f6b8 --- /dev/null +++ b/examples/ex03.yml @@ -0,0 +1,36 @@ +nodes: + X1: &boo + type: Molex Micro-Fit + gender: male + pinout: [GND, VCC] + X2: &con_power_f + type: Molex Micro-Fit + gender: female + pinout: [GND, VCC] + X3: + <<: *con_power_f + X4: + <<: *con_power_f + +wires: + W1: + type: bundle # bundles are routed together, but more loosely than normal cables + num_wires: 6 + colors: [BK, RD] # if number of items in color list is less than num_wires, loop colors + mm2: 0.25 + show_equiv: true + length: 0.2 + +connections: + - + - X1: [1-2] + - W1: [1-2] + - X2: [1-2] + - + - X1: [1-2] + - W1: [3,4] + - X3: [1-2] + - + - X1: [1-2] + - W1: [5,6] + - X4: [1-2] diff --git a/examples/ex04.gv b/examples/ex04.gv new file mode 100644 index 0000000..a191bba --- /dev/null +++ b/examples/ex04.gv @@ -0,0 +1,66 @@ +graph { +// Graph generated by WireViz +// https://github.com/formatc1702/WireViz + graph [bgcolor=transparent fontname=arial nodesep=0.33 rankdir=LR ranksep=2] + node [fillcolor=white fontname=arial shape=record style=filled] + edge [fontname=arial style=bold] + F1 [label="{crimp}|{{1}}"] + F2 [label="{crimp}|{{1}}"] + F3 [label="{crimp}|{{1}}"] + F4 [label="{crimp}|{{1}}"] + F5 [label="{crimp}|{{1}}"] + F6 [label="{crimp}|{{1}}"] + F7 [label="{crimp}|{{1}}"] + F8 [label="{crimp}|{{1}}"] + F9 [label="{crimp}|{{1}}"] + F10 [label="{crimp}|{{1}}"] + F11 [label="{crimp}|{{1}}"] + F12 [label="{crimp}|{{1}}"] + subgraph cluster_W1 { + graph [fillcolor=white label="6x | 0.25 mm² (24 AWG) | 0.2 m + " style="filled, dashed"] + node [fixedsize=true height=0 label="" shape=point width=0] + W1_w1l + W1_w1r + W1_w2l + W1_w2r + W1_w3l + W1_w3r + W1_w4l + W1_w4r + W1_w5l + W1_w5r + W1_w6l + W1_w6r + } + edge [color="#000000:#666600:#000000"] + W1_w1l -- W1_w1r [labelangle=60 labeldist=0 taillabel=" BN"] + F1:p1r -- W1_w1l:w [headlabel=" F1:1" labelangle=-60 labeldist=0] + edge [color="#000000:#ff0000:#000000"] + W1_w2l -- W1_w2r [labelangle=60 labeldist=0 taillabel=" RD"] + F2:p1r -- W1_w2l:w [headlabel=" F2:1" labelangle=-60 labeldist=0] + edge [color="#000000:#ff8000:#000000"] + W1_w3l -- W1_w3r [labelangle=60 labeldist=0 taillabel=" OG"] + F3:p1r -- W1_w3l:w [headlabel=" F3:1" labelangle=-60 labeldist=0] + edge [color="#000000:#ffff00:#000000"] + W1_w4l -- W1_w4r [labelangle=60 labeldist=0 taillabel=" YE"] + F4:p1r -- W1_w4l:w [headlabel=" F4:1" labelangle=-60 labeldist=0] + edge [color="#000000:#00ff00:#000000"] + W1_w5l -- W1_w5r [labelangle=60 labeldist=0 taillabel=" GN"] + F5:p1r -- W1_w5l:w [headlabel=" F5:1" labelangle=-60 labeldist=0] + edge [color="#000000:#0066ff:#000000"] + W1_w6l -- W1_w6r [labelangle=60 labeldist=0 taillabel=" BU"] + F6:p1r -- W1_w6l:w [headlabel=" F6:1" labelangle=-60 labeldist=0] + edge [color="#000000:#0066ff:#000000"] + W1_w6r:e -- F7:p1l [labelangle=60 labeldist=0 taillabel="F7:1 "] + edge [color="#000000:#00ff00:#000000"] + W1_w5r:e -- F8:p1l [labelangle=60 labeldist=0 taillabel="F8:1 "] + edge [color="#000000:#ffff00:#000000"] + W1_w4r:e -- F9:p1l [labelangle=60 labeldist=0 taillabel="F9:1 "] + edge [color="#000000:#ff8000:#000000"] + W1_w3r:e -- F10:p1l [labelangle=60 labeldist=0 taillabel="F10:1 "] + edge [color="#000000:#ff0000:#000000"] + W1_w2r:e -- F11:p1l [labelangle=60 labeldist=0 taillabel="F11:1 "] + edge [color="#000000:#666600:#000000"] + W1_w1r:e -- F12:p1l [labelangle=60 labeldist=0 taillabel="F12:1 "] +} diff --git a/examples/ex04.png b/examples/ex04.png new file mode 100644 index 0000000..1b1fcea Binary files /dev/null and b/examples/ex04.png differ diff --git a/examples/ex04.svg b/examples/ex04.svg new file mode 100644 index 0000000..c09923f --- /dev/null +++ b/examples/ex04.svg @@ -0,0 +1,317 @@ + + + + + + + +cluster_W1 + +6x  |  0.25 mm² (24 AWG)  |  0.2 m + + + + +F1 + +crimp + +1 + + + +W1_w1l + + + + +F1:p1r--W1_w1l:w + + + +            F1:1 + + + +F2 + +crimp + +1 + + + +W1_w2l + + + + +F2:p1r--W1_w2l:w + + + +            F2:1 + + + +F3 + +crimp + +1 + + + +W1_w3l + + + + +F3:p1r--W1_w3l:w + + + +            F3:1 + + + +F4 + +crimp + +1 + + + +W1_w4l + + + + +F4:p1r--W1_w4l:w + + + +            F4:1 + + + +F5 + +crimp + +1 + + + +W1_w5l + + + + +F5:p1r--W1_w5l:w + + + +            F5:1 + + + +F6 + +crimp + +1 + + + +W1_w6l + + + + +F6:p1r--W1_w6l:w + + + +            F6:1 + + + +F7 + +crimp + +1 + + + +F8 + +crimp + +1 + + + +F9 + +crimp + +1 + + + +F10 + +crimp + +1 + + + +F11 + +crimp + +1 + + + +F12 + +crimp + +1 + + + +W1_w1r + + + + +W1_w1l--W1_w1r + + + +                                   BN + + + +W1_w1r:e--F12:p1l + + + +F12:1             + + + +W1_w2r + + + + +W1_w2l--W1_w2r + + + +                                   RD + + + +W1_w2r:e--F11:p1l + + + +F11:1             + + + +W1_w3r + + + + +W1_w3l--W1_w3r + + + +                                   OG + + + +W1_w3r:e--F10:p1l + + + +F10:1             + + + +W1_w4r + + + + +W1_w4l--W1_w4r + + + +                                   YE + + + +W1_w4r:e--F9:p1l + + + +F9:1             + + + +W1_w5r + + + + +W1_w5l--W1_w5r + + + +                                   GN + + + +W1_w5r:e--F8:p1l + + + +F8:1             + + + +W1_w6r + + + + +W1_w6l--W1_w6r + + + +                                   BU + + + +W1_w6r:e--F7:p1l + + + +F7:1             + + + diff --git a/examples/ex04.yml b/examples/ex04.yml new file mode 100644 index 0000000..2ab5a3f --- /dev/null +++ b/examples/ex04.yml @@ -0,0 +1,32 @@ +# nodes: +# X1: +# type: D-Sub +# gender: female +# num_pins: 4 +# X2: +# type: Molex KK 254 +# gender: female +# num_pins: 3 + +wires: + W1: + mm2: 0.25 + show_equiv: true + length: 0.2 + color_code: IEC + num_wires: 6 + type: bundle + +ferrules: + ferrule_crimp: + type: crimp + show_name: false + show_num_pins: false + +connections: + - + - ferrule_crimp + - W1: [1-6] + - + - W1: [6-1] + - ferrule_crimp diff --git a/examples/example1.png b/examples/example1.png deleted file mode 100644 index ac10d2f..0000000 Binary files a/examples/example1.png and /dev/null differ diff --git a/examples/example1.py b/examples/example1.py deleted file mode 100644 index d7fd876..0000000 --- a/examples/example1.py +++ /dev/null @@ -1,15 +0,0 @@ -import wireviz - -h = wireviz.Harness() - -h.add_cable('W1', mm2=0.25, length=0.2, show_name=True, show_pinout=True, num_wires=3, color_code='DIN', shield=True) -h.add_node('X1', type='D-Sub', gender='female', pinout=('DCD','RX','TX','DTR','GND','DSR','RTS','CTS','RI')) -h.add_node('X2', type='Molex KK 254', gender='female', pinout=('GND','RX','TX','NC','OUT','IN')) -# Option 1: define wires and shield in one line -h.connect('X1',(5,2,3,5),'W1',(1,2,3,'s'),'X2',(1,3,2,None)) -h.loop('X2', 5, 6) -# Option 2: define wires and shield separately -# Harness.objects['W1'].connect('X1',(5,2,3),'auto','X2',(1,3,2)) # wires -# Harness.objects['W1'].connect('X1',(5,),('s',),'X2',(None,)) # shield - -h.output(filename='output', format=('png','svg'), view=False) diff --git a/examples/example2.png b/examples/example2.png deleted file mode 100644 index 9e88249..0000000 Binary files a/examples/example2.png and /dev/null differ diff --git a/examples/example2.py b/examples/example2.py deleted file mode 100644 index 8806c87..0000000 --- a/examples/example2.py +++ /dev/null @@ -1,31 +0,0 @@ -import wireviz - -h = wireviz.Harness() - -# shortcuts for use during harness creation -PINOUT_I2C = ('GND','+5V','SCL','SDA') -COLORS_I2C = ('BK', 'RD', 'YE', 'GN') -PINOUT_SPI_DATAONLY = ('MISO','MOSI','SCK') - -h.add_node('X1', type='Molex KK 254', gender='female', pinout=('GND', - '+5V', - 'SCL', - 'SDA', - 'MISO', - 'MOSI', - 'SCK', - 'N/C')) -h.add_node('X2', type='Molex KK 254', gender='female', pinout=PINOUT_I2C) -h.add_node('X3', type='Molex KK 254', gender='female', pinout=PINOUT_I2C) -h.add_node('X4', type='Molex KK 254', gender='female', pinout=('GND','+12V')+PINOUT_SPI_DATAONLY) -h.add_node('X5', type='Molex Micro-Fit', gender='male', pinout=('GND','+12V')) -h.add_cable('W1', mm2=0.14, show_equiv=True, length=0.2, colors=COLORS_I2C, show_name=False) -h.add_cable('W2', mm2=0.14, show_equiv=True, length=0.2, colors=COLORS_I2C, show_name=False) -h.add_cable('W3', mm2=0.14, show_equiv=True, length=0.2, colors=('BK','BU','OG','VT'), show_name=False) -h.add_cable('W4', mm2=0.5, show_equiv=True, length=0.35, colors=('BK','RD'), show_name=False) -h.connect('X1',(1,2,3,4),'W1','auto','X2','auto') -h.connect('X1',(1,2,3,4),'W2','auto','X3','auto') -h.connect('X1',(1,5,6,7),'W3','auto','X4',(1,3,4,5)) -h.connect_all_straight('W4','X5','X4') - -h.output(filename='output', format=('png','svg'), view=False) diff --git a/examples/example2.yml b/examples/example2.yml deleted file mode 100644 index 494c2b9..0000000 --- a/examples/example2.yml +++ /dev/null @@ -1,64 +0,0 @@ -templates: # defining templates to be used later on - - &molex_f - type: Molex KK 254 - gender: female - - &con_i2c - pinout: [GND, +5V, SCL, SDA] - - &wire_i2c - mm2: 0.14 - length: 0.2 - colors: [BK, RD, YE, GN] - -nodes: - X1: - <<: *molex_f # copying items from the template - pinout: [GND, +5V, SCL, SDA, MISO, MOSI, SCK, N/C] - X2: - <<: *molex_f - <<: *con_i2c # it is possible to copy from more than one template - X3: - <<: *molex_f - <<: *con_i2c - X4: - <<: *molex_f - pinout: [GND, +12V, MISO, MOSI, SCK] - X5: - type: Molex Micro-Fit - gender: male - pinout: [GND, +12V] - -wires: - W1: - <<: *wire_i2c - show_name: false - W2: - <<: *wire_i2c - show_name: false - W3: - mm2: 0.14 - length: 0.2 - colors: [BK, BU, OG, VT] - show_name: false - W4: - mm2: 0.5 - length: 0.35 - colors: [BK, RD] - show_name: false - -connections: - - - - X1: [1-4] - - W1: [1-4] - - X2: [1-4] - - - - X1: [1-4] - - W2: [1-4] - - X3: [1-4] - - - - X1: [1,5-7] - - W3: [1-4] - - X4: [1,3-5] - - - - X5: [1,2] - - W4: [1,2] - - X4: [1,2] diff --git a/examples/example3.py b/examples/example3.py deleted file mode 100644 index ef64012..0000000 --- a/examples/example3.py +++ /dev/null @@ -1,26 +0,0 @@ -import wireviz - -h = wireviz.Harness() -h.color_mode = 'full' - -h.add_node('X1', num_pins=10) -h.add_node('X2', num_pins=10) -h.add_cable('W1', num_wires=10, color_code='IEC') -h.connect_all_straight('W1','X1','X2') - -h.add_node('X3', num_pins=20) -h.add_node('X4', num_pins=20) -h.add_cable('W2', num_wires=20, color_code='DIN') -h.connect_all_straight('W2','X3','X4') - -h.add_node('X5', num_pins=20) -h.add_node('X6', num_pins=20) -h.add_cable('W3', num_wires=20, colors=('RD','YE','BU')) -h.connect_all_straight('W3','X5','X6') - -h.add_node('X7', num_pins=6) -h.add_node('X8', num_pins=6) -h.add_cable('W4', num_wires=6, length=1, mm2=1) -h.connect_all_straight('W4','X7','X8') - -h.output(filename='output', format=('png','svg'), view=False) diff --git a/examples/example4.py b/examples/example4.py deleted file mode 100644 index 97f9bb9..0000000 --- a/examples/example4.py +++ /dev/null @@ -1,13 +0,0 @@ -import wireviz - -h = wireviz.Harness() - -h.add_cable('W1', show_name=False, show_num_wires=False, num_wires=4, color_code='DIN') -h.add_cable('W2', show_name=False, show_num_wires=False, num_wires=4, color_code='DIN') -h.add_node('X1', num_pins=4, show_num_pins=False) -h.add_node('X2', num_pins=4, show_num_pins=False) -h.add_node('X3', num_pins=4, show_num_pins=False) -h.connect_all_straight('W1','X1','X2') -h.connect_all_straight('W2','X2','X3') - -h.output(filename='output', format=('png','svg'), view=False) diff --git a/examples/ferrules.yml b/examples/ferrules.yml deleted file mode 100644 index 8a88f62..0000000 --- a/examples/ferrules.yml +++ /dev/null @@ -1,34 +0,0 @@ -nodes: - X1: - type: D-Sub - gender: female - num_pins: 4 - X2: - type: Molex KK 254 - gender: female - num_pins: 3 - -wires: - W1: - mm2: 0.25 - show_equiv: true - length: 0.2 - color_code: IEC - num_wires: 10 - type: bundle - -ferrules: - F_test: - type: crimp - -connections: - - - - X1: [1-3] - - W1: [1-3] - - X2: [1-3] - - - - F_test - - W1: [4-10] - - - - W1: [10-4] - - F_test diff --git a/examples/readme.md b/examples/readme.md new file mode 100644 index 0000000..92a0c3f --- /dev/null +++ b/examples/readme.md @@ -0,0 +1,25 @@ +# Example gallery +## Example 01 +![](ex01.png) + +[Source](ex01.yml) + + +## Example 02 +![](ex02.png) + +[Source](ex02.yml) + + +## Example 03 +![](ex03.png) + +[Source](ex03.yml) + + +## Example 04 +![](ex04.png) + +[Source](ex04.yml) + + diff --git a/examples/testconnections.yml b/examples/testconnections.yml deleted file mode 100644 index ac0f9bc..0000000 --- a/examples/testconnections.yml +++ /dev/null @@ -1,43 +0,0 @@ -nodes: - X1: - # type: D-Sub - # gender: female - num_pins: 15 - X2: - type: Molex KK 254 - gender: female - num_pins: 10 - -wires: - W1: - mm2: 0.25 - length: 0.2 - color_code: DIN - num_wires: 15 - shield: true - -connections: - - - - X1: 1 - - W1: 1 - - X2: 1 - - - - X1: [2,3,4] - - W1: [2,3,4] - - X2: [4,3,2] - - - - X1: [5-10] - - W1: [5-7,10,9,8] - - X2: [10-5] - - - - X1: 11 - - W1: s - - - - X1: [1-5] - - W1: [11-15] - - - - W1: [12-15] - - X2: [2-5] - - - - X1: [12,14] - - X1: [13,15] diff --git a/readme.md b/readme.md index b9bdd78..6aba0a7 100644 --- a/readme.md +++ b/readme.md @@ -23,16 +23,17 @@ WireViz is a simple yet flexible, YAML-based markup language for documenting cab _Note_: WireViz is not designed to represent the complete wiring of a system. Its main aim is to document the construction of individual wires and harnesses. -## Example +## Examples -[WireViz input file](examples/example1.yml): +### Demo 01 + +[WireViz input file](examples/demo01.yml): nodes: X1: type: D-Sub gender: female pinout: [DCD, RX, TX, DTR, GND, DSR, RTS, CTS, RI] - random: yes X2: type: Molex KK 254 gender: female @@ -60,17 +61,22 @@ _Note_: WireViz is not designed to represent the complete wiring of a system. It Output file: -![Sample output diagram](examples/example1.png) +![Sample output diagram](examples/demo01.png) -[Example 2](examples/example2.yml) +### Demo 02 -![](examples/example2.png) +![](examples/demo02.png) + +[Source](examples/demo02.yml) + +### More examples + +See the [example gallery](examples/) and included readme file. ## Status This is very much a [work in progress](todo.md). - ## License GNU GPLv3 diff --git a/src/.gitignore b/src/.gitignore index 2d7c3ea..3000943 100644 --- a/src/.gitignore +++ b/src/.gitignore @@ -1,2 +1,2 @@ __pycache__/ -_output/ +_test/ diff --git a/src/batch.py b/src/batch.py new file mode 100644 index 0000000..19bc386 --- /dev/null +++ b/src/batch.py @@ -0,0 +1,21 @@ +import wireviz +import os + +readme = '../examples/readme.md' +readme = os.path.abspath(readme) + +with open(readme, 'w') as file: + file.write('# Example gallery\n') + for i in range(1,3): + fn = '../examples/demo{:02d}.yml'.format(i) + print(fn) + wireviz.parse(fn) + + for i in range(1,5): + fn = '../examples/ex{:02d}.yml'.format(i) + print(fn) + wireviz.parse(fn) + + file.write('## Example {:02d}\n'.format(i)) + file.write('![](ex{:02d}.png)\n\n'.format(i)) + file.write('[Source](ex{:02d}.yml)\n\n\n'.format(i)) diff --git a/src/wireviz.py b/src/wireviz.py old mode 100644 new mode 100755 index 63d803c..9f5e4a2 --- a/src/wireviz.py +++ b/src/wireviz.py @@ -1,5 +1,8 @@ +#!/usr/bin/env python3 +import os from dataclasses import dataclass, field from typing import Any, List +import yaml from graphviz import Graph COLOR_CODES = {'DIN': ['WH','BN','GN','YE','GY','PK','BU','RD','BK','VT'], # ,'GYPK','RDBU','WHGN','BNGN','WHYE','YEBN','WHGY','GYBN','WHPK','PKBN'], @@ -157,7 +160,7 @@ class Harness: if c.type == 'bundle': # create subgraph for wire bundle, add to main graph afterwards bun = Graph(name='cluster_{}'.format(k)) - labeltext = ' | '.join(p for p in a if p) + '\n ' # newline to add space between label and wires + labeltext = ' | '.join(p for p in a if p) + '\n ' # newline to add space between label and wires bun.attr('graph', label=labeltext, style='filled, dashed', fillcolor='white') @@ -385,3 +388,194 @@ def awg_equiv(mm2): return awg_equiv_table[k] else: return None + +def parse(file_in, file_out=None): + + file_in = os.path.abspath(file_in) + if not file_out: + file_out = file_in + pre, ext = os.path.splitext(file_out) + file_out = pre # extension will be added by graphviz output function + file_out = os.path.abspath(file_out) + + with open(file_in, 'r') as stream: + try: + input = yaml.safe_load(stream) + except yaml.YAMLError as exc: + print(exc) + + def expand(input): + # input can be: + # - a singleton (normally str or int) + # - a list of str or int + # if str is of the format '#-#', it is treated as a range (inclusive) and expanded + output = [] + if not isinstance(input, list): + input = [input,] + for e in input: + e = str(e) + if '-' in e: # list of pins + a, b = tuple(map(int, e.split('-'))) + if a < b: + for x in range(a,b+1): + output.append(x) + elif a > b: + for x in range(a,b-1,-1): + output.append(x) + elif a == b: + output.append(a) + else: + try: + x = int(e) + except: + x = e + output.append(x) + return output + + def check_designators(what, where): + for i, x in enumerate(what): + # print('Looking for {} in {}'.format(x,where[i])) + if x not in input[where[i]]: + return False + return True + + h = Harness() + + # add items + sections = ['nodes','wires','ferrules','connections'] + types = [dict, dict, dict, list] + for sec, ty in zip(sections, types): + if sec in input and type(input[sec]) == ty: + if len(input[sec]) > 0: + if ty == dict: + for k, o in input[sec].items(): + if sec == 'nodes': + h.add_node(name=k, **o) + elif sec == 'wires': + h.add_cable(name=k, **o) + elif sec == 'ferrules': + pass + else: + print('{} section empty'.format(sec)) + else: + print('No {} section found'.format(sec)) + if ty == dict: + input[sec] = {} + elif ty == list: + input[sec] = [] + + # add connections + ferrule_counter = 0 + for con in input['connections']: + if len(con) == 3: # format: connector -- wire -- conector + + for c in con: + if len(list(c.keys())) != 1: # check that each entry in con has only one key, which is the designator + raise Exception('Too many keys') + + from_name = list(con[0].keys())[0] + via_name = list(con[1].keys())[0] + to_name = list(con[2].keys())[0] + + if not check_designators([from_name,via_name,to_name],('nodes','wires','nodes')): + raise Exception('Bad connection definition (3)') + + from_pins = expand(con[0][from_name]) + via_pins = expand(con[1][via_name]) + to_pins = expand(con[2][to_name]) + + if len(from_pins) != len(via_pins) or len(via_pins) != len(to_pins): + raise Exception('List length mismatch') + + for (from_pin, via_pin, to_pin) in zip(from_pins, via_pins, to_pins): + h.connect(from_name, from_pin, via_name, via_pin, to_name, to_pin) + + elif len(con) == 2: + + for c in con: + if type(c) is dict: + if len(list(c.keys())) != 1: # check that each entry in con has only one key, which is the designator + raise Exception('Too many keys') + + # hack to make the format for ferrules compatible with the formats for connectors and wires + if type(con[0]) == str: + name = con[0] + con[0] = {} + con[0][name] = name + if type(con[1]) == str: + name = con[1] + con[1] = {} + con[1][name] = name + + from_name = list(con[0].keys())[0] + to_name = list(con[1].keys())[0] + + n_w = check_designators([from_name, to_name],('nodes','wires')) + w_n = check_designators([from_name, to_name],('wires','nodes')) + n_n = check_designators([from_name, to_name],('nodes','nodes')) + + + f_w = check_designators([from_name, to_name],('ferrules','wires')) + w_f = check_designators([from_name, to_name],('wires','ferrules')) + + if not n_w and not w_n and not n_n and not f_w and not w_f: + raise Exception('Wrong designators') + + from_pins = expand(con[0][from_name]) + to_pins = expand(con[1][to_name]) + + if n_w or w_n or n_n: + if len(from_pins) != len(to_pins): + raise Exception('List length mismatch') + + if n_w or w_n: + for (from_pin, to_pin) in zip(from_pins, to_pins): + if n_w: + h.connect(from_name, from_pin, to_name, to_pin, None, None) + else: # w_n + h.connect(None, None, from_name, from_pin, to_name, to_pin) + elif n_n: + con_name = list(con[0].keys())[0] + from_pins = expand(con[0][from_name]) + to_pins = expand(con[1][to_name]) + + for (from_pin, to_pin) in zip(from_pins, to_pins): + h.loop(con_name, from_pin, to_pin) + if f_w or w_f: + from_pins = expand(con[0][from_name]) + to_pins = expand(con[1][to_name]) + + if f_w: + ferrule_name = from_name + wire_name = to_name + wire_pins = to_pins + else: + ferrule_name = to_name + wire_name = from_name + wire_pins = from_pins + + ferrule_params = input['ferrules'][ferrule_name] + for wire_pin in wire_pins: + ferrule_counter = ferrule_counter + 1 + ferrule_id = 'F{}'.format(ferrule_counter) + h.add_node(ferrule_id, **ferrule_params) + + if f_w: + h.connect(ferrule_id, 1, wire_name, wire_pin, None, None) + else: + h.connect(None, None, wire_name, wire_pin, ferrule_id, 1) + + + else: + raise Exception('Wrong number of connection parameters') + + h.output(filename=file_out, format=('png','svg'), view=False) + +if __name__ == '__main__': + import argparse + ap = argparse.ArgumentParser() + ap.add_argument('file_input', nargs='?', default='_test/test.yml') + ap.add_argument('file_output', nargs='?', default=None) + args = ap.parse_args() + + parse(args.file_input, args.file_output) diff --git a/src/yaml2wireviz.py b/src/yaml2wireviz.py deleted file mode 100644 index 2275e3c..0000000 --- a/src/yaml2wireviz.py +++ /dev/null @@ -1,180 +0,0 @@ -import yaml -import wireviz - -filename = '../examples/example1.yml' -filename = '../examples/example2.yml' -filename = '../examples/ferrules.yml' -filename = '../examples/bundles.yml' - -def check_designators(what, where): - for i, x in enumerate(what): - # print('Looking for {} in {}'.format(x,where[i])) - if x not in input[where[i]]: - return False - return True - -def expand(input): - # input can be: - # - a singleton (normally str or int) - # - a list of str or int - # if str is of the format '#-#', it is treated as a range (inclusive) and expanded - output = [] - if not isinstance(input, list): - input = [input,] - for e in input: - e = str(e) - if '-' in e: # list of pins - a, b = tuple(map(int, e.split('-'))) - if a < b: - for x in range(a,b+1): - output.append(x) - elif a > b: - for x in range(a,b-1,-1): - output.append(x) - elif a == b: - output.append(a) - else: - try: - x = int(e) - except: - x = e - output.append(x) - return output - -with open(filename, 'r') as stream: - try: - input = yaml.safe_load(stream) - except yaml.YAMLError as exc: - print(exc) - -h = wireviz.Harness() - -# add items -sections = ['nodes','wires','ferrules','connections'] -types = [dict, dict, dict, list] -for sec, ty in zip(sections, types): - if sec in input and type(input[sec]) == ty: - if len(input[sec]) > 0: - if ty == dict: - for k, o in input[sec].items(): - if sec == 'nodes': - h.add_node(name=k, **o) - elif sec == 'wires': - h.add_cable(name=k, **o) - elif sec == 'ferrules': - pass - else: - print('{} section empty'.format(sec)) - else: - print('No {} section found'.format(sec)) - if ty == dict: - input[sec] = {} - elif ty == list: - input[sec] = [] - -# add connections -ferrule_counter = 0 -for con in input['connections']: - if len(con) == 3: # format: connector -- wire -- conector - - for c in con: - if len(list(c.keys())) != 1: # check that each entry in con has only one key, which is the designator - raise Exception('Too many keys') - - from_name = list(con[0].keys())[0] - via_name = list(con[1].keys())[0] - to_name = list(con[2].keys())[0] - - if not check_designators([from_name,via_name,to_name],('nodes','wires','nodes')): - raise Exception('Bad connection definition (3)') - - from_pins = expand(con[0][from_name]) - via_pins = expand(con[1][via_name]) - to_pins = expand(con[2][to_name]) - - if len(from_pins) != len(via_pins) or len(via_pins) != len(to_pins): - raise Exception('List length mismatch') - - for (from_pin, via_pin, to_pin) in zip(from_pins, via_pins, to_pins): - h.connect(from_name, from_pin, via_name, via_pin, to_name, to_pin) - - elif len(con) == 2: - - for c in con: - if type(c) is dict: - if len(list(c.keys())) != 1: # check that each entry in con has only one key, which is the designator - raise Exception('Too many keys') - - # hack to make the format for ferrules compatible with the formats for connectors and wires - if type(con[0]) == str: - name = con[0] - con[0] = {} - con[0][name] = name - if type(con[1]) == str: - name = con[1] - con[1] = {} - con[1][name] = name - - from_name = list(con[0].keys())[0] - to_name = list(con[1].keys())[0] - - n_w = check_designators([from_name, to_name],('nodes','wires')) - w_n = check_designators([from_name, to_name],('wires','nodes')) - n_n = check_designators([from_name, to_name],('nodes','nodes')) - - - f_w = check_designators([from_name, to_name],('ferrules','wires')) - w_f = check_designators([from_name, to_name],('wires','ferrules')) - - if not n_w and not w_n and not n_n and not f_w and not w_f: - raise Exception('Wrong designators') - - from_pins = expand(con[0][from_name]) - to_pins = expand(con[1][to_name]) - - if n_w or w_n or n_n: - if len(from_pins) != len(to_pins): - raise Exception('List length mismatch') - - if n_w or w_n: - for (from_pin, to_pin) in zip(from_pins, to_pins): - if n_w: - h.connect(from_name, from_pin, to_name, to_pin, None, None) - else: # w_n - h.connect(None, None, from_name, from_pin, to_name, to_pin) - elif n_n: - con_name = list(con[0].keys())[0] - from_pins = expand(con[0][from_name]) - to_pins = expand(con[1][to_name]) - - for (from_pin, to_pin) in zip(from_pins, to_pins): - h.loop(con_name, from_pin, to_pin) - if f_w or w_f: - from_pins = expand(con[0][from_name]) - to_pins = expand(con[1][to_name]) - - if f_w: - ferrule_name = from_name - wire_name = to_name - wire_pins = to_pins - else: - ferrule_name = to_name - wire_name = from_name - wire_pins = from_pins - - ferrule_params = input['ferrules'][ferrule_name] - for wire_pin in wire_pins: - ferrule_counter = ferrule_counter + 1 - ferrule_id = 'F{}'.format(ferrule_counter) - h.add_node(ferrule_id, **ferrule_params) - - if f_w: - h.connect(ferrule_id, 1, wire_name, wire_pin, None, None) - else: - h.connect(None, None, wire_name, wire_pin, ferrule_id, 1) - - - else: - raise Exception('Wrong number of connection parameters') - -h.output(filename='output', format=('png','svg'), view=False)