Add example 3
This commit is contained in:
parent
da258ceaa8
commit
5097f54d92
45
src/output/output_ex3.dot
Normal file
45
src/output/output_ex3.dot
Normal file
@ -0,0 +1,45 @@
|
|||||||
|
digraph G {
|
||||||
|
graph [rankdir = LR, ranksep=2, fontname = "arial"];
|
||||||
|
edge [arrowhead=none, fontname = "arial"];
|
||||||
|
node [shape=record, style=rounded, fontname = "arial"];
|
||||||
|
|
||||||
|
|
||||||
|
X1[label="X1 | {{|||||||||} | {<p1>1|<p2>2|<p3>3|<p4>4|<p5>5|<p6>6|<p7>7|<p8>8|<p9>9|<p10>10}}}"]
|
||||||
|
|
||||||
|
X2[label="X2 | {{<p1>1|<p2>2|<p3>3|<p4>4|<p5>5|<p6>6|<p7>7|<p8>8|<p9>9|<p10>10} | {|||||||||}}}"]
|
||||||
|
|
||||||
|
W1[label="{{<w1i>1|<w2i>2|<w3i>3|<w4i>4|<w5i>5|<w6i>6|<w7i>7|<w8i>8|<w9i>9|<w10i>10} | {BN|RD|OG|YE|GN|BU|VT|GY|WH|BK} | {<w1o>1|<w2o>2|<w3o>3|<w4o>4|<w5o>5|<w6o>6|<w7o>7|<w8o>8|<w9o>9|<w10o>10}}}"]
|
||||||
|
|
||||||
|
{edge[style=bold]
|
||||||
|
{edge[color="#000000:#808000:#000000"] X1:p1 -> W1:w1i; W1:w1o -> X2:p1}
|
||||||
|
{edge[color="#000000:#ff0000:#000000"] X1:p2 -> W1:w2i; W1:w2o -> X2:p2}
|
||||||
|
{edge[color="#000000:#ff8000:#000000"] X1:p3 -> W1:w3i; W1:w3o -> X2:p3}
|
||||||
|
{edge[color="#000000:#ffff00:#000000"] X1:p4 -> W1:w4i; W1:w4o -> X2:p4}
|
||||||
|
{edge[color="#000000:#00ff00:#000000"] X1:p5 -> W1:w5i; W1:w5o -> X2:p5}
|
||||||
|
{edge[color="#000000:#0000ff:#000000"] X1:p6 -> W1:w6i; W1:w6o -> X2:p6}
|
||||||
|
{edge[color="#000000:#8000ff:#000000"] X1:p7 -> W1:w7i; W1:w7o -> X2:p7}
|
||||||
|
{edge[color="#000000:#808080:#000000"] X1:p8 -> W1:w8i; W1:w8o -> X2:p8}
|
||||||
|
{edge[color="#000000:#ffffff:#000000"] X1:p9 -> W1:w9i; W1:w9o -> X2:p9}
|
||||||
|
{edge[color="#000000:#000000:#000000"] X1:p10 -> W1:w10i; W1:w10o -> X2:p10}
|
||||||
|
}
|
||||||
|
X3[label="X3 | {{|||||||||} | {<p1>1|<p2>2|<p3>3|<p4>4|<p5>5|<p6>6|<p7>7|<p8>8|<p9>9|<p10>10}}}"]
|
||||||
|
|
||||||
|
X4[label="X4 | {{<p1>1|<p2>2|<p3>3|<p4>4|<p5>5|<p6>6|<p7>7|<p8>8|<p9>9|<p10>10} | {|||||||||}}}"]
|
||||||
|
|
||||||
|
W2[label="{{<w1i>1|<w2i>2|<w3i>3|<w4i>4|<w5i>5|<w6i>6|<w7i>7|<w8i>8|<w9i>9|<w10i>10} | {WH|BN|GN|YE|GY|PK|BU|RD|BK|VT} | {<w1o>1|<w2o>2|<w3o>3|<w4o>4|<w5o>5|<w6o>6|<w7o>7|<w8o>8|<w9o>9|<w10o>10}}}"]
|
||||||
|
|
||||||
|
{edge[style=bold]
|
||||||
|
{edge[color="#000000:#ffffff:#000000"] X3:p1 -> W2:w1i; W2:w1o -> X4:p1}
|
||||||
|
{edge[color="#000000:#808000:#000000"] X3:p2 -> W2:w2i; W2:w2o -> X4:p2}
|
||||||
|
{edge[color="#000000:#00ff00:#000000"] X3:p3 -> W2:w3i; W2:w3o -> X4:p3}
|
||||||
|
{edge[color="#000000:#ffff00:#000000"] X3:p4 -> W2:w4i; W2:w4o -> X4:p4}
|
||||||
|
{edge[color="#000000:#808080:#000000"] X3:p5 -> W2:w5i; W2:w5o -> X4:p5}
|
||||||
|
{edge[color="#000000:#ff80c0:#000000"] X3:p6 -> W2:w6i; W2:w6o -> X4:p6}
|
||||||
|
{edge[color="#000000:#0000ff:#000000"] X3:p7 -> W2:w7i; W2:w7o -> X4:p7}
|
||||||
|
{edge[color="#000000:#ff0000:#000000"] X3:p8 -> W2:w8i; W2:w8o -> X4:p8}
|
||||||
|
{edge[color="#000000:#000000:#000000"] X3:p9 -> W2:w9i; W2:w9o -> X4:p9}
|
||||||
|
{edge[color="#000000:#8000ff:#000000"] X3:p10 -> W2:w10i; W2:w10o -> X4:p10}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
}
|
||||||
57
src/test.py
57
src/test.py
@ -16,29 +16,40 @@ PINOUT_SPI_DATAONLY = ('MISO','MOSI','SCK')
|
|||||||
# objects = [X1, X2, W1]
|
# objects = [X1, X2, W1]
|
||||||
|
|
||||||
# example 2
|
# example 2
|
||||||
X1 = wireviz.Node("X1", pinout=(
|
# X1 = wireviz.Node("X1", pinout=(
|
||||||
'GND',
|
# 'GND',
|
||||||
'+5V',
|
# '+5V',
|
||||||
'SCL',
|
# 'SCL',
|
||||||
'SDA',
|
# 'SDA',
|
||||||
'MISO',
|
# 'MISO',
|
||||||
'MOSI',
|
# 'MOSI',
|
||||||
'SCK',
|
# 'SCK',
|
||||||
'N/C'
|
# 'N/C'
|
||||||
), ports_right=True)
|
# ), ports_right=True)
|
||||||
X2 = wireviz.Node("X2", pinout=PINOUT_I2C, ports_left=True)
|
# X2 = wireviz.Node("X2", pinout=PINOUT_I2C, ports_left=True)
|
||||||
X3 = wireviz.Node("X3", pinout=PINOUT_I2C, ports_left=True)
|
# X3 = wireviz.Node("X3", pinout=PINOUT_I2C, ports_left=True)
|
||||||
X4 = wireviz.Node("X4", pinout=('GND','+12V')+PINOUT_SPI_DATAONLY, ports_left=True)
|
# X4 = wireviz.Node("X4", pinout=('GND','+12V')+PINOUT_SPI_DATAONLY, ports_left=True)
|
||||||
X5 = wireviz.Node("X5", pinout=('GND','+12V'), ports_right=True)
|
# X5 = wireviz.Node("X5", pinout=('GND','+12V'), ports_right=True)
|
||||||
W1 = wireviz.Cable("W1", colors=COLORS_I2C)
|
# W1 = wireviz.Cable("W1", colors=COLORS_I2C)
|
||||||
W2 = wireviz.Cable("W2", colors=COLORS_I2C)
|
# W2 = wireviz.Cable("W2", colors=COLORS_I2C)
|
||||||
W3 = wireviz.Cable("W3", colors=('BK','BU','OG','VT'))
|
# W3 = wireviz.Cable("W3", colors=('BK','BU','OG','VT'))
|
||||||
W4 = wireviz.Cable("W4", colors=('BK','RD'))
|
# W4 = wireviz.Cable("W4", colors=('BK','RD'))
|
||||||
W1.connect(X1,(1,2,3,4),'auto',X2,'auto')
|
# W1.connect(X1,(1,2,3,4),'auto',X2,'auto')
|
||||||
W2.connect(X1,(1,2,3,4),'auto',X3,'auto')
|
# W2.connect(X1,(1,2,3,4),'auto',X3,'auto')
|
||||||
W3.connect(X1,(1,5,6,7),'auto',X4,(1,3,4,5))
|
# W3.connect(X1,(1,5,6,7),'auto',X4,(1,3,4,5))
|
||||||
W4.connect(X5,'auto','auto',X4,'auto')
|
# W4.connect(X5,'auto','auto',X4,'auto')
|
||||||
objects = [X1, X2, X3, X4, X5, W1, W2, W3, W4]
|
# objects = [X1, X2, X3, X4, X5, W1, W2, W3, W4]
|
||||||
|
|
||||||
|
# example 3
|
||||||
|
X1 = wireviz.Node("X1", num_pins=10, ports_right=True)
|
||||||
|
X2 = wireviz.Node("X2", num_pins=10, ports_left=True)
|
||||||
|
W1 = wireviz.Cable("W1", num_wires=10, color_code="IEC")
|
||||||
|
W1.connect_all_straight(X1,X2)
|
||||||
|
X3 = wireviz.Node("X3", num_pins=10, ports_right=True)
|
||||||
|
X4 = wireviz.Node("X4", num_pins=10, ports_left=True)
|
||||||
|
W2 = wireviz.Cable("W2", num_wires=10, color_code="DIN")
|
||||||
|
W2.connect_all_straight(X3,X4)
|
||||||
|
objects = [X1, X2, W1, X3, X4, W2]
|
||||||
|
|
||||||
with open('output/output.dot','w') as f:
|
with open('output/output.dot','w') as f:
|
||||||
with open('input/header.dot','r') as infile:
|
with open('input/header.dot','r') as infile:
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user