Remove idea directory

This commit is contained in:
Daniel Rojas 2020-05-30 12:12:38 +02:00
parent d86ec0ad68
commit e7c95e4aa9
5 changed files with 0 additions and 110 deletions

View File

@ -1,29 +0,0 @@
// Graph generated by WireViz
// https://github.com/formatc1702/WireViz
// Daniel Rojas - 2020
digraph G {
graph [rankdir = LR, ranksep=2, fontname = "arial"];
edge [arrowhead=none, fontname = "arial"];
node [shape=record, style=rounded, fontname = "arial"];
X1[label="X1 | {D-Sub|female|9-pin} | {{DCD|RX|TX|DTR|GND|DSR|RTS|CTS|RI} | {<p1>1|<p2>2|<p3>3|<p4>4|<p5>5|<p6>6|<p7>7|<p8>8|<p9>9}}}"]
X2[label="X2 | {Molex KK 254|female|6-pin} | {{<p1>1|<p2>2|<p3>3|<p4>4|<p5>5|<p6>6} | {GND|RX|TX|NC|OUT|IN}}}"]
{edge[style=bold]
X2:p5:w -> X2:p6:w
}
W1[label="W1 | {3x|0.25 mm²| + S|0.2 m} | {{<w1i>1|<w2i>2|<w3i>3|<wsi>} | {WH|BN|GN|Shield} | {<w1o>1|<w2o>2|<w3o>3|<wso>}}}"]
{edge[style=bold]
{edge[color="#000000:#ffffff:#000000"] X1:p5 -> W1:w1i; W1:w1o -> X2:p1}
{edge[color="#000000:#666600:#000000"] X1:p2 -> W1:w2i; W1:w2o -> X2:p3}
{edge[color="#000000:#00ff00:#000000"] X1:p3 -> W1:w3i; W1:w3o -> X2:p2}
{X1:p5 -> W1:wsi; }
}
}

Binary file not shown.

Before

Width:  |  Height:  |  Size: 151 KiB

View File

@ -1,28 +0,0 @@
// define connectors
X1 [type="D-Sub",
gender="female",
pin_labels="DCD|RX|TX|DTR|GND|DSR|RTS|CTS|RI",
]
X2 [type="Molex KK 254",
gender="female",
pin_labels="GND|RX|TX|NC|OUT|IN",
]
// define wire
W1 [mm2=0.25,
length=0.2,
num_wires=3,
colors="din47100",
shield=true
]
// define connections
X1:5 -> W1:1 -> X2:1 // GND
X1:2 -> W1:2 -> X2:3 // TX-RX
X1:3 -> W1:3 -> X2:2 // RX-TX
X1:5 -> W1:S // shield
X2:5 -> X2:6 // loop

View File

@ -1,53 +0,0 @@
// Graph generated by WireViz
// https://github.com/formatc1702/WireViz
// Daniel Rojas - 2020
digraph G {
graph [rankdir = LR, ranksep=2, fontname = "arial"];
edge [arrowhead=none, fontname = "arial"];
node [shape=record, style=rounded, fontname = "arial"];
X1[label="X1 | {Molex KK 254|female|8-pin} | {{GND|+5V|SCL|SDA|MISO|MOSI|SCK|N/C} | {<p1>1|<p2>2|<p3>3|<p4>4|<p5>5|<p6>6|<p7>7|<p8>8}}}"]
X2[label="X2 | {Molex KK 254|female|4-pin} | {{<p1>1|<p2>2|<p3>3|<p4>4} | {GND|+5V|SCL|SDA}}}"]
X3[label="X3 | {Molex KK 254|female|4-pin} | {{<p1>1|<p2>2|<p3>3|<p4>4} | {GND|+5V|SCL|SDA}}}"]
X4[label="X4 | {Molex KK 254|female|5-pin} | {{<p1>1|<p2>2|<p3>3|<p4>4|<p5>5} | {GND|+12V|MISO|MOSI|SCK}}}"]
X5[label="X5 | {Molex Micro-Fit|male|2-pin} | {{GND|+12V} | {<p1>1|<p2>2}}}"]
W1[label="{4x|0.14 mm²|0.2 m} | {{<w1>BK|<w2>RD|<w3>YE|<w4>GN}}}"]
{edge[style=bold]
{edge[color="#000000:#000000:#000000"] X1:p1 -> W1:w1; W1:w1 -> X2:p1}
{edge[color="#000000:#ff0000:#000000"] X1:p2 -> W1:w2; W1:w2 -> X2:p2}
{edge[color="#000000:#ffff00:#000000"] X1:p3 -> W1:w3; W1:w3 -> X2:p3}
{edge[color="#000000:#00ff00:#000000"] X1:p4 -> W1:w4; W1:w4 -> X2:p4}
}
W2[label="{4x|0.14 mm²|0.2 m} | {{<w1>BK|<w2>RD|<w3>YE|<w4>GN}}}"]
{edge[style=bold]
{edge[color="#000000:#000000:#000000"] X1:p1 -> W2:w1; W2:w1 -> X3:p1}
{edge[color="#000000:#ff0000:#000000"] X1:p2 -> W2:w2; W2:w2 -> X3:p2}
{edge[color="#000000:#ffff00:#000000"] X1:p3 -> W2:w3; W2:w3 -> X3:p3}
{edge[color="#000000:#00ff00:#000000"] X1:p4 -> W2:w4; W2:w4 -> X3:p4}
}
W3[label="{4x|0.14 mm²|0.2 m} | {{<w1>BK|<w2>BU|<w3>OG|<w4>VT}}}"]
{edge[style=bold]
{edge[color="#000000:#000000:#000000"] X1:p1 -> W3:w1; W3:w1 -> X4:p1}
{edge[color="#000000:#0000ff:#000000"] X1:p5 -> W3:w2; W3:w2 -> X4:p3}
{edge[color="#000000:#ff8000:#000000"] X1:p6 -> W3:w3; W3:w3 -> X4:p4}
{edge[color="#000000:#8000ff:#000000"] X1:p7 -> W3:w4; W3:w4 -> X4:p5}
}
W4[label="{2x|0.5 mm²|0.35 m} | {{<w1>BK|<w2>RD}}}"]
{edge[style=bold]
{edge[color="#000000:#000000:#000000"] X5:p1 -> W4:w1; W4:w1 -> X4:p1}
{edge[color="#000000:#ff0000:#000000"] X5:p2 -> W4:w2; W4:w2 -> X4:p2}
}
}

Binary file not shown.

Before

Width:  |  Height:  |  Size: 382 KiB