Auto-decide connector pin side based on wiring

This commit is contained in:
Daniel Rojas 2020-05-24 14:44:19 +02:00
parent 2b955fa10c
commit f0724ede3f
5 changed files with 44 additions and 35 deletions

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@ -99,7 +99,6 @@ The parser will follow later; contributions are welcome!
## To do
* Automate creation of left/right side ports for connectors
* Add simple connectors (ferrules, cable lugs)
* no pinout
* graphical representation?

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@ -3,8 +3,8 @@ import wireviz
h = wireviz.Harness()
h.add_cable('W1', mm2=0.25, length=0.2, show_name=True, show_pinout=True, num_wires=3, color_code='DIN', shield=True)
h.add_node('X1', type='D-Sub', gender='female', pinout=('DCD','RX','TX','DTR','GND','DSR','RTS','CTS','RI'), ports_right=True)
h.add_node('X2', type='Molex KK 254', gender='female', pinout=('GND','RX','TX','NC','OUT','IN'), ports_left=True)
h.add_node('X1', type='D-Sub', gender='female', pinout=('DCD','RX','TX','DTR','GND','DSR','RTS','CTS','RI'))
h.add_node('X2', type='Molex KK 254', gender='female', pinout=('GND','RX','TX','NC','OUT','IN'))
# Option 1: define wires and shield in one line
h.connect('W1','X1',(5,2,3,5),(1,2,3,'s'),'X2',(1,3,2,None))
h.loop('X2', 5, 6)

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@ -14,11 +14,11 @@ h.add_node('X1',type='Molex KK 254', gender='female', pinout=('GND',
'MISO',
'MOSI',
'SCK',
'N/C'), ports_right=True)
h.add_node('X2', type='Molex KK 254', gender='female', pinout=PINOUT_I2C, ports_left=True)
h.add_node('X3', type='Molex KK 254', gender='female', pinout=PINOUT_I2C, ports_left=True)
h.add_node('X4', type='Molex KK 254', gender='female', pinout=('GND','+12V')+PINOUT_SPI_DATAONLY, ports_left=True)
h.add_node('X5', type='Molex Micro-Fit', gender='male', pinout=('GND','+12V'), ports_right=True)
'N/C'))
h.add_node('X2', type='Molex KK 254', gender='female', pinout=PINOUT_I2C)
h.add_node('X3', type='Molex KK 254', gender='female', pinout=PINOUT_I2C)
h.add_node('X4', type='Molex KK 254', gender='female', pinout=('GND','+12V')+PINOUT_SPI_DATAONLY)
h.add_node('X5', type='Molex Micro-Fit', gender='male', pinout=('GND','+12V'))
h.add_cable('W1', mm2=0.14, show_equiv=True, length=0.2, colors=COLORS_I2C, show_name=False)
h.add_cable('W2', mm2=0.14, show_equiv=True, length=0.2, colors=COLORS_I2C, show_name=False)
h.add_cable('W3', mm2=0.14, show_equiv=True, length=0.2, colors=('BK','BU','OG','VT'), show_name=False)

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@ -3,23 +3,23 @@ import wireviz
h = wireviz.Harness()
h.color_mode = 'full'
h.add_node('X1', num_pins=10, ports_right=True)
h.add_node('X2', num_pins=10, ports_left=True)
h.add_node('X1', num_pins=10)
h.add_node('X2', num_pins=10)
h.add_cable('W1', num_wires=10, color_code='IEC')
h.connect_all_straight('W1','X1','X2')
h.add_node('X3', num_pins=20, ports_right=True)
h.add_node('X4', num_pins=20, ports_left=True)
h.add_node('X3', num_pins=20)
h.add_node('X4', num_pins=20)
h.add_cable('W2', num_wires=20, color_code='DIN')
h.connect_all_straight('W2','X3','X4')
h.add_node('X5', num_pins=20, ports_right=True)
h.add_node('X6', num_pins=20, ports_left=True)
h.add_node('X5', num_pins=20)
h.add_node('X6', num_pins=20)
h.add_cable('W3', num_wires=20, colors=('RD','YE','BU'))
h.connect_all_straight('W3','X5','X6')
h.add_node('X7', num_pins=6, ports_right=True)
h.add_node('X8', num_pins=6, ports_left=True)
h.add_node('X7', num_pins=6)
h.add_node('X8', num_pins=6)
h.add_cable('W4', num_wires=6, length=1, mm2=1)
h.connect_all_straight('W4','X7','X8')

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@ -63,8 +63,8 @@ class Harness:
def add_cable(self, name, mm2=None, awg=None, show_equiv=False, length=0, show_name=False, show_pinout=False, num_wires=None, colors=None, color_code=None, shield=False):
self.cables[name] = Cable(name, mm2, awg, show_equiv, length, show_name, show_pinout, num_wires, colors, color_code, shield)
def loop(self, node_name, from_pin, to_pin, side=None):
self.nodes[node_name].loop(from_pin, to_pin, side)
def loop(self, node_name, from_pin, to_pin):
self.nodes[node_name].loop(from_pin, to_pin)
def connect(self, cable_name, from_name, from_pin, via, to_name, to_pin):
self.cables[cable_name].connect(from_name, from_pin, via, to_name, to_pin)
@ -81,6 +81,15 @@ class Harness:
dot.attr('node', shape='record', style='rounded,filled', fillcolor='white', fontname=font)
dot.attr('edge', style='bold', fontname=font)
# prepare ports on connectors depending on which side they will connect
for k in self.cables:
c = self.cables[k]
for x in c.connections:
if x[1] is not None: # connect to left
self.nodes[x[0]].ports_right = True
if x[4] is not None: # connect to right
self.nodes[x[3]].ports_left = True
for k in self.nodes:
n = self.nodes[k]
# a = attributes
@ -90,18 +99,26 @@ class Harness:
p[1] = list(n.pinout)
for i,x in enumerate(n.pinout, 1):
if n.ports_left == True:
p[0].append('<p{portno}>{portno}'.format(portno=i))
p[0].append('<p{portno}l>{portno}'.format(portno=i))
if n.ports_right == True:
p[2].append('<p{portno}>{portno}'.format(portno=i))
p[2].append('<p{portno}r>{portno}'.format(portno=i))
# l = label
l = [n.name if n.show_name == True else '', a, p]
dot.node(k, label=nested(l))
if len(n.loops) > 0:
dot.attr('edge',color='#000000')
if n.ports_left == True:
loop_side = 'l'
loop_dir = 'w'
elif n.ports_right == True:
loop_side = 'r'
loop_dir = 'e'
else:
raise Exception('No side for loops')
for x in n.loops:
dot.edge('{name}:p{port_from}:{loop_side}'.format(name=n.name, port_from=x[0], port_to=x[1], loop_side=x[2]),
'{name}:p{port_to}:{loop_side}'.format(name=n.name, port_from=x[0], port_to=x[1], loop_side=x[2]))
dot.edge('{name}:p{port_from}{loop_side}:{loop_dir}'.format(name=n.name, port_from=x[0], port_to=x[1], loop_side=loop_side, loop_dir=loop_dir),
'{name}:p{port_to}{loop_side}:{loop_dir}'.format(name=n.name, port_from=x[0], port_to=x[1], loop_side=loop_side, loop_dir=loop_dir))
for k in self.cables:
c = self.cables[k]
@ -142,11 +159,13 @@ class Harness:
else: # it's a shield connection
dot.attr('edge',color='#000000')
if x[1] is not None: # connect to left
dot.edge('{from_name}:p{from_port}'.format(from_name=x[0],from_port=x[1]),
dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]),
'{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='i' if c.show_pinout == True else ''))
# self.nodes[x[0]].ports_right = True
if x[4] is not None: # connect to right
dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='o' if c.show_pinout == True else ''),
'{to_name}:p{to_port}'.format(to_name=x[3], to_port=x[4]))
'{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4]))
# self.nodes[x[3]].ports_left = True
return dot
@ -177,17 +196,8 @@ class Node:
else:
self.pinout = pinout
def loop(self, from_pin, to_pin, side=None):
if self.ports_left == True and self.ports_right == False:
loop_side = 'w' # west = left
elif self.ports_left == False and self.ports_right == True:
loop_side = 'e' # east = right
elif self.ports_left == True and self.ports_right == True:
if side == None:
raise Exception('Must specify side of loop')
else:
loop_side = side
self.loops.append((from_pin, to_pin, loop_side))
def loop(self, from_pin, to_pin):
self.loops.append((from_pin, to_pin))
class Cable: