warehack.ing/WireViz
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Show from/to designators on wire bundle

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This commit is contained in:
Daniel Rojas 2020-05-29 22:55:39 +02:00
parent 12b4746e01
commit fcf67145bf
2 changed files with 11 additions and 7 deletions
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3
examples/bundles.yml
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@ -36,7 +36,7 @@ wires:
type: bundle type: bundle
W3: W3:
mm2: 0.14 mm2: 0.14
# length: 0.2 length: 0.2
type: bundle type: bundle
colors: [BK, BU, OG, VT] colors: [BK, BU, OG, VT]
W4: W4:
@ -44,7 +44,6 @@ wires:
length: 0.35 length: 0.35
colors: [BK, RD] colors: [BK, RD]
type: bundle type: bundle
show_num_wires: false
connections: connections:
- -

15
src/wireviz.py
View File

@ -195,21 +195,26 @@ class Harness:
'{via_name}_w{via_wire}r'.format(via_name=c.name, via_wire=x[2]), '{via_name}_w{via_wire}r'.format(via_name=c.name, via_wire=x[2]),
taillabel=labeltext, taillabel=labeltext,
labelangle='60', labelangle='60',
labeldist='0', labeldist='0')
labelfloat='true')
existing_connections.append(x[2]) existing_connections.append(x[2])
if x[1] is not None: # connect to left if x[1] is not None: # connect to left
if c.type == 'bundle': if c.type == 'bundle':
dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]), dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]),
'{via_name}_w{via_wire}l:w'.format(via_name=c.name, via_wire=x[2])) '{via_name}_w{via_wire}l:w'.format(via_name=c.name, via_wire=x[2]),
headlabel='{}{}:{}'.format(' ' * 12,x[0],x[1]),
labelangle='-60',
labeldist='0')
else: else:
dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]), dot.edge('{from_name}:p{from_port}r'.format(from_name=x[0],from_port=x[1]),
'{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='i' if c.show_pinout else '')) '{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='i' if c.show_pinout else ''))
if x[4] is not None: # connect to right if x[4] is not None: # connect to right
if c.type == 'bundle': if c.type == 'bundle':
dot.edge('{via_name}_w{via_wire}r:e'.format(via_name=c.name, via_wire=x[2]), dot.edge('{via_name}_w{via_wire}r:e'.format(via_name=c.name, via_wire=x[2]),
'{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4])) '{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4]),
taillabel='{}:{}{}'.format(x[3],x[4],' ' * 12),
labelangle='60',
labeldist='0')
else: else:
dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='o' if c.show_pinout else ''), dot.edge('{via_name}:w{via_wire}{via_subport}'.format(via_name=c.name, via_wire=x[2], via_subport='o' if c.show_pinout else ''),
'{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4])) '{to_name}:p{to_port}l'.format(to_name=x[3], to_port=x[4]))
@ -333,7 +338,7 @@ def translate_color(input, color_mode):
if color_mode == 'full': if color_mode == 'full':
output = color_full[input].lower() output = color_full[input].lower()
elif color_mode == 'FULL': elif color_mode == 'FULL':
output = color_hex[input].upper() output = color_full[input].upper()
elif color_mode == 'hex': elif color_mode == 'hex':
output = color_hex[input].lower() output = color_hex[input].lower()
elif color_mode == 'HEX': elif color_mode == 'HEX':