Ryan Malloy 7f81c1f4ce Prove channel packing: connects all where greedy drops, feasibility-bounded
Add channel_pack.dsn: three nets whose pads spread wider than a wall gap, so they
must converge and pack into lanes. Plain room routing (shove on or off) drops >= 1
net under every net ordering; the packer connects all three under every ordering,
DRC-clean (search tree and independent emitted-copper check).

The falsifiable boundary test sweeps the gap width for N=3 and N=4 and asserts the
packer connects all N iff the gap meets the geometric feasibility width
(N-1)*(width+clearance) + 2*(half_width+clearance), never routes fewer than greedy
below it, and never false-packs. Determinism, endpoints-on-pads, valid SES, and
pack=False-equals-default (additive) are covered.
2026-07-13 12:27:31 -06:00
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DSN test fixtures

Hand-crafted minimal Specctra DSN files, written to exercise the parser. They are modeled on the real fixtures shipped in the upstream FreeRouting repo (fixtures/empty_board.dsn and fixtures/SMD-routing-issue-demo.dsn) so the grammar and formatting match what kicad-cli pcb export specctra-dsn and FreeRouting itself produce, but they were typed fresh here (no upstream file is copied into this tree).

  • empty_board.dsn — the smallest valid board: parser, resolution, unit, and a structure with two signal layers and a pcb boundary path. Modeled on FreeRouting fixtures/empty_board.dsn.
  • smd_demo.dsn — a fuller board exercising every scope the parser handles: quoted board/padstack/image names, via, default rule (width + clearance with a (type smd_smd) pair), a keepout, padstacks (rect and circle pads), images with pins, placement with front/rotation, nets with Comp-Pin references, and a class with circuit/use_via and a rule. Modeled on FreeRouting fixtures/SMD-routing-issue-demo.dsn.