Ryan Malloy
7f81c1f4ce
Add channel_pack.dsn: three nets whose pads spread wider than a wall gap, so they must converge and pack into lanes. Plain room routing (shove on or off) drops >= 1 net under every net ordering; the packer connects all three under every ordering, DRC-clean (search tree and independent emitted-copper check). The falsifiable boundary test sweeps the gap width for N=3 and N=4 and asserts the packer connects all N iff the gap meets the geometric feasibility width (N-1)*(width+clearance) + 2*(half_width+clearance), never routes fewer than greedy below it, and never false-packs. Determinism, endpoints-on-pads, valid SES, and pack=False-equals-default (additive) are covered.
76 lines
1.3 KiB
Plaintext
76 lines
1.3 KiB
Plaintext
(pcb "channel_pack.dsn"
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(parser
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(string_quote ")
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(space_in_quoted_tokens on)
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(host_cad "freeroute-test")
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(host_version "1.0")
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)
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(resolution um 10)
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(unit um)
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(structure
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(layer F.Cu
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(type signal)
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(property
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(index 0)
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)
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)
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(layer B.Cu
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(type power)
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(property
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(index 1)
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)
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)
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(boundary
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(path pcb 0 0 0 200000 0 200000 -80000 0 -80000 0 0)
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)
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(keepout "wall_left"
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(rect F.Cu 0 -42000 92000 -38000)
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)
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(keepout "wall_right"
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(rect F.Cu 108000 -42000 200000 -38000)
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)
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(rule
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(width 2000)
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(clearance 2000)
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)
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)
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(library
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(padstack Rect_Pad
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(shape (rect F.Cu -1000 -1000 1000 1000))
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(attach off)
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)
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(image PAD
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(pin Rect_Pad 1 0 0)
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)
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)
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(placement
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(component PAD
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(place P0a 70000 -10000 front 0)
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(place P0b 70000 -70000 front 0)
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(place P1a 100000 -10000 front 0)
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(place P1b 100000 -70000 front 0)
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(place P2a 130000 -10000 front 0)
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(place P2b 130000 -70000 front 0)
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)
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)
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(network
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(net NET0
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(pins P0a-1 P0b-1)
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)
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(net NET1
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(pins P1a-1 P1b-1)
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)
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(net NET2
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(pins P2a-1 P2b-1)
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)
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(class default
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(rule
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(width 2000)
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(clearance 2000)
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)
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)
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)
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(wiring
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)
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)
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