Ryan Malloy
49c258e81d
Adds crossing_2net.dsn: NET_A is a full-width horizontal wall and NET_B's pins sit above and below it, so single-layer routing cannot connect NET_B but two-layer routing succeeds by dipping to the other layer through vias. Tests assert the multi-layer invariants: single-layer routing leaves a net unrouted with no vias; multi-layer connects both nets with >= 1 via; the SES contains a via scope; every via sits at a real layer transition of its net's path; trace/via endpoints still land on the pads; traces stay on valid layers and within the outline; and no two different nets cross on the same layer. Oracle-gated parity tests cover the simple and crossing boards.
74 lines
1.3 KiB
Plaintext
74 lines
1.3 KiB
Plaintext
(pcb "crossing_2net.dsn"
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(parser
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(string_quote ")
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(space_in_quoted_tokens on)
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(host_cad "freeroute-test")
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(host_version "1.0")
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)
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(resolution um 10)
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(unit um)
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(structure
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(layer Top
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(type signal)
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(property
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(index 0)
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)
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)
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(layer Bottom
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(type signal)
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(property
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(index 1)
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)
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)
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(boundary
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(path pcb 0 0 0 200000 0 200000 -80000 0 -80000 0 0)
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)
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(via "Via[0-1]_600:300_um")
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(rule
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(width 2000)
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(clearance 2000)
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)
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)
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(library
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(padstack Rect_Pad
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(shape (rect Top -1000 -1000 1000 1000))
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(attach off)
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)
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(padstack "Via[0-1]_600:300_um"
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(shape (circle Top 600))
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(shape (circle Bottom 600))
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(attach off)
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)
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(image PAD
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(pin Rect_Pad 1 0 0)
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)
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)
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(placement
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(component PAD
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(place A1 2000 -40000 front 0)
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(place A2 198000 -40000 front 0)
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(place B1 100000 -15000 front 0)
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(place B2 100000 -65000 front 0)
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)
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)
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(network
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(net NET_A
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(pins A1-1 A2-1)
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)
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(net NET_B
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(pins B1-1 B2-1)
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)
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(class default
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(circuit
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(use_via "Via[0-1]_600:300_um")
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)
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(rule
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(width 2000)
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(clearance 2000)
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)
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)
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)
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(wiring
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)
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)
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