Ryan Malloy
da91382015
Adds ripup_needed.dsn: one signal layer (B.Cu is a power plane, so vias are impossible) with two nets whose greedy order strands NET_B, but where rip-up reroutes NET_A around NET_B to connect both. Tests: greedy (rip_up=False) leaves >= 1 connection unrouted with no vias; rip-up connects all with no vias; the result is deterministic across re-runs; rip-up keeps endpoints on pads and produces no same-layer cross between nets (ripped traces leave no orphaned occupancy). The crossing board's single-layer test now targets the greedy path explicitly, and a regression test asserts the real KiCad board still connects all four of its multi-pin nets. Oracle-gated parity added for the congested board.
65 lines
1.0 KiB
Plaintext
65 lines
1.0 KiB
Plaintext
(pcb "ripup_needed.dsn"
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(parser
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(string_quote ")
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(space_in_quoted_tokens on)
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(host_cad "freeroute-test")
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(host_version "1.0")
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)
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(resolution um 10)
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(unit um)
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(structure
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(layer F.Cu
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(type signal)
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(property
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(index 0)
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)
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)
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(layer B.Cu
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(type power)
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(property
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(index 1)
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)
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)
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(boundary
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(path pcb 0 0 0 200000 0 200000 -80000 0 -80000 0 0)
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)
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(rule
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(width 2000)
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(clearance 2000)
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)
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)
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(library
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(padstack Rect_Pad
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(shape (rect F.Cu -1000 -1000 1000 1000))
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(attach off)
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)
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(image PAD
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(pin Rect_Pad 1 0 0)
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)
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)
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(placement
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(component PAD
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(place A1 2000 -40000 front 0)
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(place A2 198000 -40000 front 0)
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(place B1 100000 -15000 front 0)
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(place B2 100000 -65000 front 0)
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)
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)
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(network
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(net NET_A
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(pins A1-1 A2-1)
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)
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(net NET_B
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(pins B1-1 B2-1)
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)
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(class default
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(rule
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(width 2000)
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(clearance 2000)
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)
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)
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)
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(wiring
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)
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)
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