Keepout exits and rule areas
A route may not leave a cell inside a wire keepout as a wire, nor reach a pin there by one: it changes layer instead, and the via goes in the pad. A pin whose every stub enters a keepout is reached by a via only. A structure keepout named rule_area... (mckicad names KiCad rule areas so) is checked for overlap only, as KiCad's DRC does, with the free ends of each wire tested for their round caps.
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@@ -254,3 +254,37 @@ def test_via_size_comes_from_the_via_padstack():
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from freeroute.route.pipeline import _via_half_board
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assert _via_half_board(parse_dsn(_PAD_DSN), 10) == 3000 # 0.6 mm via, board units
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# --- rule areas: overlap only ------------------------------------------------
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_CHANNEL_DSN = """(pcb channel.dsn
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(parser (string_quote ")) (resolution um 10) (unit um)
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(structure
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(layer F.Cu (type signal)) (layer B.Cu (type signal))
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(boundary (path pcb 0 0 0 40000 0 40000 -30000 0 -30000 0 0))
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(keepout "{name}top" (polygon signal 0 18000 0 22000 0 22000 -14750 18000 -14750))
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(keepout "{name}bottom" (polygon signal 0 18000 -15250 22000 -15250 22000 -30000 18000 -30000))
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(rule (width 250) (clearance 150)))
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(placement (component P (place P1 5000 -15000 front 0) (place P2 35000 -15000 front 0)))
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(library (image P (pin pad 1 0 0)) (padstack pad (shape (circle F.Cu 600)) (attach off)))
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(network (net N (pins P1-1 P2-1))))"""
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def test_a_keepout_named_rule_area_takes_no_clearance():
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named = _areas(_CHANNEL_DSN.format(name="rule_area_"))
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plain = _areas(_CHANNEL_DSN.format(name=""))
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assert named and not any(a.clearance for a in named)
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assert plain and all(a.clearance for a in plain)
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def _route_channel(name):
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from freeroute.route.pipeline import build_exact_routing_result
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return build_exact_routing_result(parse_dsn(_CHANNEL_DSN.format(name=name)), resolution=2)
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def test_a_trace_may_run_beside_a_rule_area_closer_than_clearance():
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# the 0.5 mm channel fits a 0.25 mm trace, but not with 0.15 mm each side
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assert _route_channel("rule_area_").unrouted == []
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assert _route_channel("").unrouted != []
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