Add crossing fixture and multi-layer/via routing tests

Adds crossing_2net.dsn: NET_A is a full-width horizontal wall and NET_B's pins sit above and below it, so single-layer routing cannot connect NET_B but two-layer routing succeeds by dipping to the other layer through vias. Tests assert the multi-layer invariants: single-layer routing leaves a net unrouted with no vias; multi-layer connects both nets with >= 1 via; the SES contains a via scope; every via sits at a real layer transition of its net's path; trace/via endpoints still land on the pads; traces stay on valid layers and within the outline; and no two different nets cross on the same layer. Oracle-gated parity tests cover the simple and crossing boards.
2026-07-12 13:21:00 -06:00
parent 992bba82a0
commit 49c258e81d
2 changed files with 218 additions and 70 deletions
@@ -0,0 +1,73 @@
+(pcb "crossing_2net.dsn"
+  (parser
+    (string_quote ")
+    (space_in_quoted_tokens on)
+    (host_cad "freeroute-test")
+    (host_version "1.0")
+  )
+  (resolution um 10)
+  (unit um)
+  (structure
+    (layer Top
+      (type signal)
+      (property
+        (index 0)
+      )
+    )
+    (layer Bottom
+      (type signal)
+      (property
+        (index 1)
+      )
+    )
+    (boundary
+      (path pcb 0  0 0  200000 0  200000 -80000  0 -80000  0 0)
+    )
+    (via "Via[0-1]_600:300_um")
+    (rule
+      (width 2000)
+      (clearance 2000)
+    )
+  )
+  (library
+    (padstack Rect_Pad
+      (shape (rect Top -1000 -1000 1000 1000))
+      (attach off)
+    )
+    (padstack "Via[0-1]_600:300_um"
+      (shape (circle Top 600))
+      (shape (circle Bottom 600))
+      (attach off)
+    )
+    (image PAD
+      (pin Rect_Pad 1 0 0)
+    )
+  )
+  (placement
+    (component PAD
+      (place A1 2000 -40000 front 0)
+      (place A2 198000 -40000 front 0)
+      (place B1 100000 -15000 front 0)
+      (place B2 100000 -65000 front 0)
+    )
+  )
+  (network
+    (net NET_A
+      (pins A1-1 A2-1)
+    )
+    (net NET_B
+      (pins B1-1 B2-1)
+    )
+    (class default
+      (circuit
+        (use_via "Via[0-1]_600:300_um")
+      )
+      (rule
+        (width 2000)
+        (clearance 2000)
+      )
+    )
+  )
+  (wiring
+  )
+)