Prove channel packing: connects all where greedy drops, feasibility-bounded

Add channel_pack.dsn: three nets whose pads spread wider than a wall gap, so they
must converge and pack into lanes. Plain room routing (shove on or off) drops >= 1
net under every net ordering; the packer connects all three under every ordering,
DRC-clean (search tree and independent emitted-copper check).

The falsifiable boundary test sweeps the gap width for N=3 and N=4 and asserts the
packer connects all N iff the gap meets the geometric feasibility width
(N-1)*(width+clearance) + 2*(half_width+clearance), never routes fewer than greedy
below it, and never false-packs. Determinism, endpoints-on-pads, valid SES, and
pack=False-equals-default (additive) are covered.

tests/dsn/fixtures/channel_pack.dsn

@@ -0,0 +1,75 @@
+(pcb "channel_pack.dsn"
+  (parser
+    (string_quote ")
+    (space_in_quoted_tokens on)
+    (host_cad "freeroute-test")
+    (host_version "1.0")
+  )
+  (resolution um 10)
+  (unit um)
+  (structure
+    (layer F.Cu
+      (type signal)
+      (property
+        (index 0)
+      )
+    )
+    (layer B.Cu
+      (type power)
+      (property
+        (index 1)
+      )
+    )
+    (boundary
+      (path pcb 0  0 0  200000 0  200000 -80000  0 -80000  0 0)
+    )
+    (keepout "wall_left"
+      (rect F.Cu 0 -42000 92000 -38000)
+    )
+    (keepout "wall_right"
+      (rect F.Cu 108000 -42000 200000 -38000)
+    )
+    (rule
+      (width 2000)
+      (clearance 2000)
+    )
+  )
+  (library
+    (padstack Rect_Pad
+      (shape (rect F.Cu -1000 -1000 1000 1000))
+      (attach off)
+    )
+    (image PAD
+      (pin Rect_Pad 1 0 0)
+    )
+  )
+  (placement
+    (component PAD
+      (place P0a 70000 -10000 front 0)
+      (place P0b 70000 -70000 front 0)
+      (place P1a 100000 -10000 front 0)
+      (place P1b 100000 -70000 front 0)
+      (place P2a 130000 -10000 front 0)
+      (place P2b 130000 -70000 front 0)
+    )
+  )
+  (network
+    (net NET0
+      (pins P0a-1 P0b-1)
+    )
+    (net NET1
+      (pins P1a-1 P1b-1)
+    )
+    (net NET2
+      (pins P2a-1 P2b-1)
+    )
+    (class default
+      (rule
+        (width 2000)
+        (clearance 2000)
+      )
+    )
+  )
+  (wiring
+  )
+)