Route to the real board outline, per connection, and out of fine-pitch pins

- The exact engine verified copper per net and dropped a whole net on any
  conflict: a 25-pin +3V3 net lost every connection to one bad segment.
  Verify and accept per ratsnest connection instead.
- Pad and keepout cells were rounded outward, blocking cells up to half a
  step clear of the copper; 62 of the 64 pins of a 0.5 mm pitch LQFP could
  not start a route. Block only cells whose centre is inside the clearance
  zone, and let a net walk along inside its own pad, which adds no copper.
- Routing was bounded by the outline's bounding box, so tracks cut across
  rounded corners. Keep the DSN boundary as a polygon; the grid blocks cells
  too close to it (scanline plus per-edge, precomputed for vias) and the
  exact and room engines reject copper that is.
- --edge-clearance MM sets copper-to-edge clearance, e.g. KiCad's
  min_copper_edge_clearance, which the DSN does not carry. Default 0.

On the TerraHawk rc4 power stage the exact engine now matches the
FreeRouting JAR: same open count, no DRC errors, with a 0.5 mm edge rule.

src/freeroute/board/board.py

@@ -22,7 +22,7 @@ __all__ = ["BasicBoard"]
 class BasicBoard:
     """A board: layers, nets, clearances, a bounding box, and items."""
 
-    __slots__ = ("layer_structure", "nets", "clearance_matrix", "bounding_box", "_items")
+    __slots__ = ("layer_structure", "nets", "clearance_matrix", "bounding_box", "outline", "_items")
 
     def __init__(
         self,
@@ -35,6 +35,8 @@ class BasicBoard:
         self.nets = nets
         self.clearance_matrix = clearance_matrix
         self.bounding_box = bounding_box
+        #: the real board outline, when the DSN has a polygon boundary
+        self.outline = None
         self._items: list[Item] = []
 
     # --- layers -------------------------------------------------------------