Route to the real board outline, per connection, and out of fine-pitch pins
- The exact engine verified copper per net and dropped a whole net on any conflict: a 25-pin +3V3 net lost every connection to one bad segment. Verify and accept per ratsnest connection instead. - Pad and keepout cells were rounded outward, blocking cells up to half a step clear of the copper; 62 of the 64 pins of a 0.5 mm pitch LQFP could not start a route. Block only cells whose centre is inside the clearance zone, and let a net walk along inside its own pad, which adds no copper. - Routing was bounded by the outline's bounding box, so tracks cut across rounded corners. Keep the DSN boundary as a polygon; the grid blocks cells too close to it (scanline plus per-edge, precomputed for vias) and the exact and room engines reject copper that is. - --edge-clearance MM sets copper-to-edge clearance, e.g. KiCad's min_copper_edge_clearance, which the DSN does not carry. Default 0. On the TerraHawk rc4 power stage the exact engine now matches the FreeRouting JAR: same open count, no DRC errors, with a 0.5 mm edge rule.
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@@ -91,6 +91,7 @@ def route_board_exact(
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max_shove_depth: int = 5,
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shove_cap: int = 3,
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via_half: int | None = None,
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edge_clearance: int | None = None,
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) -> ExactRouteResult:
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"""Route ``board`` orthogonally and verify the result with exact geometry.
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@@ -116,7 +117,10 @@ def route_board_exact(
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rip_up=rip_up,
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orthogonal=True,
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via_half=via_half,
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edge_clearance=edge_clearance,
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)
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edge = 0 if edge_clearance is None else edge_clearance
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outline = board.outline
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tree = ShapeSearchTree()
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owner = _counter()
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@@ -143,20 +147,25 @@ def route_board_exact(
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via_layers = frozenset(signal_layers)
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accepted: dict[int, _Accepted] = {}
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for net_no in sorted(set(result.wires) | set(result.vias)):
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boxes = _net_boxes(result, net_no, half_width, via_layers, via_half)
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# Verify connection by connection, so one conflicting segment of a
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# 25-pin supply net costs that one connection, not the whole net.
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for net_no, wires, vias in sorted(result.connections, key=lambda c: c[0]):
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boxes = _copper_boxes(wires, vias, half_width, via_layers, via_half)
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if any(
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tree.clearance_conflict(box, net_no, layer, clearance)
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for box, box_layers in boxes
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for layer in box_layers
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):
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) or (outline is not None and not all(outline.box_clear(b, edge) for b, _ in boxes)):
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continue # exact-clearance conflict -> drop (may be recovered by shove)
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acc = _Accepted(wires=result.wires.get(net_no, []), vias=result.vias.get(net_no, []))
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acc = accepted.get(net_no)
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if acc is None:
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acc = accepted[net_no] = _Accepted(wires=[], vias=[])
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acc.wires.extend(wires)
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acc.vias.extend(vias)
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for box, box_layers in boxes:
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oid = next(owner)
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tree.insert(TreeShape(oid, net_no, box_layers, box, routed=True))
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acc.owners.append(oid)
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accepted[net_no] = acc
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# a net is dropped if it has a real ratsnest (>= 2 pins on a signal layer)
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# but was not accepted — whether the grid failed to route it or its exact
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@@ -547,12 +556,18 @@ def _rollback(shoved, accepted, tree, owner) -> int: # noqa: ARG001
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def _net_boxes(result, net_no, half_width, via_layers, via_half=None):
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return _copper_boxes(
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result.wires.get(net_no, []), result.vias.get(net_no, []), half_width, via_layers, via_half
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)
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def _copper_boxes(wires, vias, half_width, via_layers, via_half=None):
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via_half = via_half or half_width
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boxes: list[tuple[IntBox, frozenset[int]]] = []
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for layer, points in result.wires.get(net_no, []):
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for layer, points in wires:
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for box in PolylineShape(Polyline(points), half_width).tiles():
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boxes.append((box, frozenset({layer})))
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for loc in result.vias.get(net_no, []):
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for loc in vias:
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vbox = IntBox(loc.x - via_half, loc.y - via_half, loc.x + via_half, loc.y + via_half)
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boxes.append((vbox, via_layers))
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return boxes
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