Add congested fixture and rip-up-and-retry tests

Adds ripup_needed.dsn: one signal layer (B.Cu is a power plane, so vias
are impossible) with two nets whose greedy order strands NET_B, but where
rip-up reroutes NET_A around NET_B to connect both.

Tests: greedy (rip_up=False) leaves >= 1 connection unrouted with no vias;
rip-up connects all with no vias; the result is deterministic across
re-runs; rip-up keeps endpoints on pads and produces no same-layer cross
between nets (ripped traces leave no orphaned occupancy). The crossing
board's single-layer test now targets the greedy path explicitly, and a
regression test asserts the real KiCad board still connects all four of
its multi-pin nets. Oracle-gated parity added for the congested board.

tests/dsn/fixtures/ripup_needed.dsn

@@ -0,0 +1,64 @@
+(pcb "ripup_needed.dsn"
+  (parser
+    (string_quote ")
+    (space_in_quoted_tokens on)
+    (host_cad "freeroute-test")
+    (host_version "1.0")
+  )
+  (resolution um 10)
+  (unit um)
+  (structure
+    (layer F.Cu
+      (type signal)
+      (property
+        (index 0)
+      )
+    )
+    (layer B.Cu
+      (type power)
+      (property
+        (index 1)
+      )
+    )
+    (boundary
+      (path pcb 0  0 0  200000 0  200000 -80000  0 -80000  0 0)
+    )
+    (rule
+      (width 2000)
+      (clearance 2000)
+    )
+  )
+  (library
+    (padstack Rect_Pad
+      (shape (rect F.Cu -1000 -1000 1000 1000))
+      (attach off)
+    )
+    (image PAD
+      (pin Rect_Pad 1 0 0)
+    )
+  )
+  (placement
+    (component PAD
+      (place A1 2000 -40000 front 0)
+      (place A2 198000 -40000 front 0)
+      (place B1 100000 -15000 front 0)
+      (place B2 100000 -65000 front 0)
+    )
+  )
+  (network
+    (net NET_A
+      (pins A1-1 A2-1)
+    )
+    (net NET_B
+      (pins B1-1 B2-1)
+    )
+    (class default
+      (rule
+        (width 2000)
+        (clearance 2000)
+      )
+    )
+  )
+  (wiring
+  )
+)