freeroute ignored the DSN's planes (KiCad's zones), so it never knew that
pads in a pour are joined by it. On the rc4 power stage those pads sit
inside "keep router off" areas as well, and every connection to them was
dropped without a word.
- Read (plane <net> <shape>) and put each zone on the board as a
ConductionArea of its net. Zones are not obstacles: KiCad refills them
around other nets' copper.
- The grid groups each net's pads and zone pieces that copper already
joins (a pad in a zone, two zones sharing a pad) and routes only between
groups. A connection may end on a zone by a via inside its copper, or by
a track where tracks are allowed.
- wire_keepout now blocks traces only, as KiCad's "no tracks" rule area
does; via_keepout only vias; keepout both, in the grid and in the exact
verifier.
rc4 power stage, exact engine, resolution 2: 2 unconnected, down from 8
(FreeRouting JAR: 12), no DRC errors.
Add optional exact/seg fields to TreeShape for a diagonal trace tile: tile holds
the bounding box for broad-phase bucketing, exact holds the tight octagon copper,
and seg=(a,b,half_width) rebuilds the clearance region on demand. Every
orthogonal tile leaves both None and takes the identical box code path, so the
box-only tree stays byte-for-byte unchanged (whole suite green).
clearance_conflict now tests a stored diagonal tile with an exact 2-D overlap;
clearance_conflict_shape checks a diagonal trace's clearance octagon against
stored copper; has_violation runs the exact octagon test whenever either tile is
diagonal and the plain box overlap otherwise. All exact-integer via Simplex
intersection.
A bounding-box spatial hash (broad phase) with exact IntBox-intersection
narrow phase, replacing the exact router's occupancy grid. Supports
insert/remove-owner and overlap/region queries, a clearance_conflict test
(strict 2-D overlap of the clearance-expanded box, so tiles exactly a
clearance apart are allowed), and has_violation for the whole-board DRC
check. Tiles are tagged routed vs static so pad-vs-pad spacing in the
source design is not counted as a routing violation.