"""Net classes wider than the default are routed at their width where it fits."""

from __future__ import annotations

from freeroute.dsn import parse_dsn
from freeroute.route.pipeline import build_exact_routing_result

_BOARD = """(pcb widths (parser) (resolution um 10) (unit um)
  (structure
    (layer F.Cu (type signal))
    (boundary (path pcb 0  0 0  20000 0  20000 -10000  0 -10000  0 0))
    {keepouts}
    (rule (width 150) (clearance 150)))
  (placement (component S (place P1 2000 -5000 front 0) (place P2 18000 -5000 front 0)))
  (library (image S (pin pad 1 0 0)) (padstack pad (shape (rect F.Cu -600 -600 600 600)) (attach off)))
  (network (net PWR (pins P1-1 P2-1))
    (class Power PWR (rule (width 400) (clearance 150)))))"""

# two keepouts leave a 0.65 mm channel: room for 0.15 mm (0.45), not for 0.4 mm (0.7)
_CHANNEL = (
    '(keepout "" (polygon F.Cu 0  9000 0  11000 0  11000 -4675  9000 -4675))\n'
    '    (keepout "" (polygon F.Cu 0  9000 -5325  11000 -5325  11000 -10000  9000 -10000))'
)


def _route(keepouts=""):
    return build_exact_routing_result(parse_dsn(_BOARD.format(keepouts=keepouts)), resolution=2)


def test_a_wider_class_is_routed_and_written_at_its_width():
    result = _route()
    assert result.unrouted == [] and result.narrowed == []
    widths = {w.width for net in result.nets for w in net.wires}
    assert widths == {400.0}


def test_a_wider_class_that_does_not_fit_falls_back_to_the_default():
    result = _route(_CHANNEL)
    assert result.unrouted == []
    assert [net for net, _a, _b in result.narrowed] == ["PWR"]
    widths = {w.width for net in result.nets for w in net.wires}
    assert widths == {150.0}