rsp2k
8b3ebc53cf
A 1.0 mm trace from a 1.27 mm pitch pin (the RN2483 row on the TTN Enschede mote) has to stay within 0.06 mm of the pin's centreline until it is past the neighbouring pads. No grid column is that close, and the router could not get there: - A stub ran as one slanted segment to its cell centre. The exact check sees that as its bounding box, which lands on the next pad. Orthogonal stubs now leave straight along the pin's axis and jog to the cell only at the end. - End nodes were chosen as in free space even in the rip-up search, so once another net crossed a pin's only exit, the pin had no end left and rip-up could never take the exit back. In rip-up mode those cells and stubs are now enterable at the rip penalty, and routes on a stub are ripped along with the ones the path crosses. - Two neighbouring pins' stubs each claim the cells a centred trace would crowd, so their claims overlapped well before their copper did. Stub against stub is now checked on the copper. - Escapes also look one column either side, so two pins leaving the same way can jog apart. TTN Enschede mote, exact engine with --shove: 12 unrouted before, 0 after; KiCad DRC on the result has no clearance violations and no unconnected items. The 0.5 mm pitch row test at resolution 1 now routes all 5 pins (it pinned 2).
255 lines
12 KiB
Python
255 lines
12 KiB
Python
"""Routing behaviours found on the TerraHawk rc4 boards (2026-09-27)."""
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from __future__ import annotations
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import math
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import pytest
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from freeroute.board import build_board
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from freeroute.dsn import parse_dsn
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from freeroute.route.pipeline import route_dsn_board_exact
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# 20 x 20 mm board whose corners are rounded with a 3 mm radius, as polylines
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_R = 3000.0
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_arc = [(_R - _R * math.cos(math.radians(a)), _R - _R * math.sin(math.radians(a))) for a in range(0, 91, 15)]
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def _outline_coords():
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pts = []
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for cx, cy, sx, sy in ((0, 0, 1, 1), (20000, 0, -1, 1), (20000, -20000, -1, -1), (0, -20000, 1, -1)):
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corner = [(cx + sx * x, cy - sy * y) for x, y in _arc]
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pts.extend(corner if sx * sy > 0 else corner[::-1])
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return " ".join(f"{x:.1f} {y:.1f}" for x, y in pts)
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def _dsn(placement, network, extra=""):
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return f"""(pcb t (parser) (resolution um 10) (unit um)
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(structure (layer F.Cu (type signal)) (layer B.Cu (type signal))
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(boundary (path pcb 0 {_outline_coords()}))
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(via "Via[0-1]_600:300_um") (rule (width 250) (clearance 150)) {extra})
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(placement {placement})
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(library (image P (pin pad 1 0 0))
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(padstack pad (shape (rect F.Cu -150 -500 150 500)) (attach off))
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(padstack "Via[0-1]_600:300_um" (shape (circle F.Cu 600)) (shape (circle B.Cu 600)) (attach off)))
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(network {network}))"""
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def test_routes_keep_edge_clearance_at_a_rounded_corner():
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# two pads near the top-left corner: the direct path cuts the corner arc
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text = _dsn("(component P (place A 1800 -6000 front 0) (place B 6000 -1800 front 90))",
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"(net N (pins A-1 B-1))")
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dsn = parse_dsn(text)
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result, scale, _ = route_dsn_board_exact(dsn, edge_clearance_mm=0.5)
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assert result.routed_net_numbers
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outline = build_board(dsn).outline
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half = 125 * scale
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for segs in result.result.wires.values():
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for _layer, pts in segs:
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for p in pts:
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# every trace point, plus half the trace, keeps 0.5 mm to the edge
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assert outline.edge_distance(p) >= half + 500 * scale - 1
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@pytest.mark.parametrize("resolution", [1, 4])
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def test_every_pin_of_a_half_millimetre_pitch_row_escapes(resolution):
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# Five 0.3 mm pads at 0.5 mm pitch, each wired to its own pad 8 mm away.
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# Between two neighbours a trace's centre has a legal band only 0.15 mm
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# wide. At resolution 4 the 0.1 mm columns cannot miss it. At resolution
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# 1 the 0.4 mm grid misses most bands, but a stub leaves its pin straight
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# along the band and jogs to the column only past the pads, so every pin
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# gets out there too, as the JAR manages (only 2 did before).
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places = " ".join(f"(place R{i} {6000 + 500 * i} -6000 front 0)" for i in range(5))
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places += " " + " ".join(f"(place F{i} {6000 + 500 * i} -14000 front 0)" for i in range(5))
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nets = " ".join(f"(net N{i} (pins R{i}-1 F{i}-1))" for i in range(5))
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result, _, _ = route_dsn_board_exact(
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parse_dsn(_dsn(f"(component P {places})", nets)), resolution=resolution
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)
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assert len(result.routed_net_numbers) == 5
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assert result.drc_clean
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def test_resolution_one_has_no_halo_so_the_grid_is_unchanged():
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from freeroute.route.grid_router import GridRouter
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board = build_board(parse_dsn(_dsn("", "")))
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assert GridRouter(board, trace_width=2500, clearance=1500)._halo_offsets == []
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fine = GridRouter(board, trace_width=2500, clearance=1500, resolution=2)
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assert fine.step == 2000 and (1, 0) in fine._halo_offsets and (2, 0) not in fine._halo_offsets
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def test_heuristic_weight_bounds_route_length():
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# weighted A* may take a longer route, but never more than W times the shortest
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places = "(place A 3000 -3000 front 0) (place B 17000 -17000 front 0)"
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def length(weight):
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result, _, _ = route_dsn_board_exact(
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parse_dsn(_dsn(f"(component P {places})", "(net N (pins A-1 B-1))")),
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heuristic_weight=weight,
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)
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return sum(
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math.hypot(q.x - p.x, q.y - p.y)
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for segs in result.result.wires.values()
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for _layer, pts in segs
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for p, q in zip(pts, pts[1:], strict=False)
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)
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shortest = length(1.0)
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assert shortest > 0
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assert length(2.0) <= 2.0 * shortest
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# --- copper zones (DSN planes) -----------------------------------------------
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# rc4 power stage: pads inside "keep router off" pours connect through the pour,
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# and freeroute, not knowing zones, dropped every such connection.
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_ZONE = "(plane N (polygon F.Cu 0 4000 -4000 10000 -4000 10000 -10000 4000 -10000 4000 -4000))"
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_NO_TRACKS = "(wire_keepout \"pour\" (polygon F.Cu 0 4000 -4000 10000 -4000 10000 -10000 4000 -10000))"
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def _zone_board():
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places = "(place P1 5500 -7000 front 0) (place P2 8500 -7000 front 0) (place P3 16000 -16000 front 0)"
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return parse_dsn(_dsn(f"(component P {places})", "(net N (pins P1-1 P2-1 P3-1))", _ZONE + " " + _NO_TRACKS))
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def test_planes_are_read_and_are_not_obstacles():
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dsn = _zone_board()
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assert [(p.net, p.shape.layer) for p in dsn.planes] == [("N", "F.Cu")]
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board = build_board(dsn)
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assert len(board.get_conduction_areas()) == 1
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assert all(not a.is_obstacle() or a.name == "pour" for a in board.get_obstacle_areas())
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def test_pads_in_one_zone_need_no_route_between_them():
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from freeroute.route.grid_router import _connected_groups
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board = build_board(_zone_board())
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pins = sorted(board.get_pins(), key=lambda p: p.component_ref)
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groups = _connected_groups(pins, board.get_conduction_areas())
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assert [sorted(p.component_ref for p in g[0]) for g in groups] == [["P1", "P2"], ["P3"]]
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def test_a_pad_reaches_a_zone_under_a_no_tracks_area_by_a_via():
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dsn = _zone_board()
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result, scale, names = route_dsn_board_exact(dsn)
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net = next(iter(result.routed_net_numbers))
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assert result.result.vias.get(net) # it had to drop into the zone
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board = build_board(dsn)
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pour = next(a for a in board.get_obstacle_areas() if a.name == "pour")
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f_cu = names.index("F.Cu")
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for layer, pts in result.result.wires[net]:
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if layer == f_cu: # no track runs inside the no-tracks area
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assert not any(t.contains(p) and not t.bounding_box().is_empty()
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for t in pour.tiles for p in pts[1:-1])
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def test_a_pour_other_nets_can_cross_is_not_trusted_to_connect():
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# the same zone with no no-tracks area over it: its fill could be split by
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# other nets' tracks, so its pads are joined by routing, not assumed
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places = "(place P1 5500 -7000 front 0) (place P2 8500 -7000 front 0)"
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dsn = parse_dsn(_dsn(f"(component P {places})", "(net N (pins P1-1 P2-1))", _ZONE))
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result, _, _ = route_dsn_board_exact(dsn)
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net = next(iter(result.routed_net_numbers))
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assert result.result.wires.get(net) # P1 and P2 got a track between them
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def test_cli_names_the_connections_it_could_not_route(tmp_path, capsys):
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# a keepout wall across the board on both layers: A and B cannot be joined
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from freeroute.cli import main
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wall = " ".join(
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f"(keepout \"wall\" (polygon {layer} 0 9000 1000 11000 1000 11000 -21000 9000 -21000))"
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for layer in ("F.Cu", "B.Cu")
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)
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dsn = tmp_path / "wall.dsn"
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dsn.write_text(_dsn("(component P (place A 4000 -10000 front 0) (place B 16000 -10000 front 0))",
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"(net N (pins A-1 B-1))", wall))
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assert main([str(dsn), "--engine", "exact", "-do", str(tmp_path / "out.ses")]) == 0
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err = capsys.readouterr().err
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assert "1 connection(s) not routed" in err and "N: A-1 to B-1" in err
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# --- inner plane layers (a 4-layer board with a GND plane on In1.Cu) --------
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def _four_layer_dsn():
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return """(pcb four (parser) (resolution um 10) (unit um)
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(structure
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(layer F.Cu (type signal)) (layer In1.Cu (type power))
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(layer In2.Cu (type power)) (layer B.Cu (type signal))
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(boundary (path pcb 0 0 0 30000 0 30000 -30000 0 -30000 0 0))
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(plane GND (polygon In1.Cu 0 500 -500 29500 -500 29500 -29500 500 -29500 500 -500))
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(via "Via[0-3]_600:300_um") (rule (width 250) (clearance 150)))
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(placement
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(component S (place G1 5000 -5000 front 0) (place G2 25000 -5000 front 0)
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(place G3 15000 -25000 front 0) (place A 5000 -15000 front 0) (place B 25000 -15000 front 0))
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(component T (place GT 15000 -15000 front 0)))
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(library
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(image S (pin smd 1 0 0))
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(image T (pin tht 1 0 0))
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(padstack smd (shape (rect F.Cu -300 -300 300 300)) (attach off))
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(padstack tht (shape (circle F.Cu 1000)) (shape (circle B.Cu 1000)) (attach off))
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(padstack "Via[0-3]_600:300_um" (shape (circle F.Cu 600)) (shape (circle B.Cu 600)) (attach off)))
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(network (net GND (pins G1-1 G2-1 G3-1 GT-1)) (net SIG (pins A-1 B-1))))"""
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def test_smd_pads_reach_an_inner_plane_by_their_own_via():
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dsn = parse_dsn(_four_layer_dsn())
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result, scale, names = route_dsn_board_exact(dsn)
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gnd = next(i + 1 for i, n in enumerate(dsn.nets) if n.name == "GND")
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sig = next(i + 1 for i, n in enumerate(dsn.nets) if n.name == "SIG")
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assert len(result.result.vias.get(gnd, [])) == 3 # one per SMD pad, none for the THT pad
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for _layer, pts in result.result.wires.get(gnd, []): # stubs, not tracks across the board
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length = sum(abs(q.x - p.x) + abs(q.y - p.y) for p, q in zip(pts, pts[1:], strict=False))
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assert length < 3000 * scale # under 3 mm: a stub to its via
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assert sig in result.result.routed_net_numbers # signals still route on the outer layers
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assert all(names[layer] in ("F.Cu", "B.Cu") for segs in result.result.wires.values() for layer, _ in segs)
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def test_a_pad_outside_the_plane_routes_to_it():
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# G1 sits left of a plane that covers only the right half, so its route
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# has to reach the plane's cells: those ends are the plane, not a pin
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dsn_text = _four_layer_dsn().replace(
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"(plane GND (polygon In1.Cu 0 500 -500 29500 -500 29500 -29500 500 -29500 500 -500))",
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"(plane GND (polygon In1.Cu 0 15000 -500 29500 -500 29500 -29500 15000 -29500 15000 -500))",
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)
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result, _scale, _names = route_dsn_board_exact(parse_dsn(dsn_text))
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gnd = next(i + 1 for i, n in enumerate(parse_dsn(dsn_text).nets) if n.name == "GND")
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assert gnd in result.result.routed_net_numbers
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def test_a_through_hole_pad_inside_a_plane_needs_no_route():
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from freeroute.route.grid_router import _connected_groups
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board = build_board(parse_dsn(_four_layer_dsn()))
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plane = [z for z in board.get_conduction_areas() if z.name == "GND"]
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gnd_pins = [p for p in board.get_pins() if p.component_ref in ("G1", "G2", "G3", "GT")]
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groups = _connected_groups(gnd_pins, plane, frozenset(id(z) for z in plane))
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hub = next(g for g in groups if g[1])
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assert [p.component_ref for p in hub[0]] == ["GT"]
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def test_a_pad_inside_a_via_keepout_reaches_the_plane_by_a_via_outside_it():
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# a sensor's GND pad: vias are forbidden under the body, so the route
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# has to leave on the top layer and drop to the plane past the keepout
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dsn = parse_dsn("""(pcb repro (parser) (resolution um 10) (unit um)
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(structure
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(layer F.Cu (type signal)) (layer In1.Cu (type power)) (layer In2.Cu (type power))
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(layer B.Cu (type signal))
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(boundary (path pcb 0 0 0 20000 0 20000 -20000 0 -20000 0 0))
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(plane GND (polygon In1.Cu 0 500 -500 19500 -500 19500 -19500 500 -19500 500 -500))
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(via_keepout "" (polygon signal 0 8500 -8500 11500 -8500 11500 -11500 8500 -11500 8500 -8500))
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(via "Via[0-3]_600:300_um") (rule (width 150) (clearance 150)))
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(placement (component S (place G1 10000 -10000 front 0)))
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(library
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(image S (pin smd 1 0 0))
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(padstack smd (shape (rect F.Cu -175 -300 175 300)) (attach off))
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(padstack "Via[0-3]_600:300_um" (shape (circle F.Cu 600)) (shape (circle B.Cu 600)) (attach off)))
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(network (net GND (pins G1-1))))""")
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exact, scale, _names = route_dsn_board_exact(dsn, resolution=2)
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assert exact.result.failed == []
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(via,) = exact.result.vias[1]
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half = 300 * scale # the via's radius
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outside = (via.x + half <= 8500 * scale or via.x - half >= 11500 * scale
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or via.y - half >= -8500 * scale or via.y + half <= -11500 * scale)
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assert outside, f"via at {via} is inside the via keepout"
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