Every pin of a supply drops its own via to the plane, and nothing kept two of them apart: the flight controller came back with 199 co-located holes and 109 hole-to-hole errors, nearly all VDD_3V3 and GND. A via now keeps its drill plus --hole-to-hole (default 0.25 mm, KiCad's) from every via centre, fixed ones included, except an own-net via at the same cell, which it reuses; such a via is written once, and none is written on top of a via already on the board.
37 lines
1.6 KiB
Python
37 lines
1.6 KiB
Python
"""Vias keep hole-to-hole spacing, even within one net."""
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from __future__ import annotations
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import itertools
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import math
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from freeroute.dsn import parse_dsn
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from freeroute.route.pipeline import route_dsn_board_exact
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# four GND pads 0.5 mm apart over a GND plane: each drops a via to the plane
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_DSN = """(pcb holes (parser) (resolution um 10) (unit um)
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(structure
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(layer F.Cu (type signal)) (layer In1.Cu (type power)) (layer In2.Cu (type power))
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(layer B.Cu (type signal))
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(boundary (path pcb 0 0 0 20000 0 20000 -20000 0 -20000 0 0))
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(plane GND (polygon In1.Cu 0 500 -500 19500 -500 19500 -19500 500 -19500 500 -500))
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(via "Via[0-3]_500:300_um") (rule (width 150) (clearance 150)))
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(placement (component S (place G1 9000 -10000 front 0) (place G2 9500 -10000 front 0)
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(place G3 10000 -10000 front 0) (place G4 10500 -10000 front 0)))
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(library
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(image S (pin smd 1 0 0))
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(padstack smd (shape (rect F.Cu -150 -300 150 300)) (attach off))
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(padstack "Via[0-3]_500:300_um" (shape (circle F.Cu 500)) (shape (circle B.Cu 500)) (attach off)))
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(network (net GND (pins G1-1 G2-1 G3-1 G4-1))))"""
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def test_a_nets_own_vias_keep_hole_to_hole_spacing():
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dsn = parse_dsn(_DSN)
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exact, scale, _ = route_dsn_board_exact(dsn, resolution=2)
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assert exact.result.failed == []
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vias = exact.result.vias[1]
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assert len(set(vias)) == len(vias), "a via written twice"
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need = (300 + 250) * scale # drill + 0.25 mm, centre to centre
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for a, b in itertools.combinations(vias, 2):
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assert math.hypot(a.x - b.x, a.y - b.y) >= need, f"vias at {a} and {b} too close"
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