Update EEPROM recovery guide with I2C bus latch root cause
Replaces speculative "corrupted boot data" with confirmed I2C bus latch diagnosis from 100+ failed power cycle attempts. Mark Option D (wait + watch) as exhausted. Add pending firmware fixes table for post-recovery testing.
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@ -12,10 +12,34 @@ corrupted firmware from EEPROM, preventing USB enumeration.
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## Root Cause
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The EEPROM (24C128 at I2C 0x51) likely has corrupted boot data. The
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FX2LP boot ROM reads the EEPROM at power-up and hangs if the C2 image
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has invalid load record lengths or addresses. The boot ROM occupies
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the 8051 core, preventing USB control transfer processing.
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The FX2LP boot ROM reads EEPROM (24C128 at I2C 0x51) at power-up.
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The I2C bus is shared with the BCM3440 tuner and BCM4500 demod. Two
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failure modes cause the hang:
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1. **I2C bus latch** (confirmed): The BCM4500 or BCM3440 holds SDA
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LOW from a prior incomplete transaction. I2C is open-drain — any
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device sinking SDA prevents all communication. The boot ROM loops
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waiting for ACK from the EEPROM, which can never respond because
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SDA is stuck.
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2. **Corrupted C2 image** (possible): If the EEPROM's C2 header is
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intact but load records have invalid lengths or addresses, the boot
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ROM hangs mid-load.
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Either way, the boot ROM occupies the 8051 core and never reaches
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the USB enumeration handler. The D+ pull-up activates (hub sees the
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device as "present") but descriptor reads time out.
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**Tested and failed (2025-02-19/20):**
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- 100+ USB power cycles via uhubctl (varied off-times: 0.2s to 30s)
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- Host-side I2C manipulation via 0xA0 vendor commands
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- xHCI controller reset, port deauthorization
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- Ultra-rapid cycling (0.2-1.0s off)
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- Historically ~3-6% success rate on power cycles, now 0%
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The I2C bus state degrades with each failed attempt. Software-only
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recovery is not viable. Physical intervention (Options A or B) is
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required.
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## Recovery Options (pick one)
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@ -92,10 +116,10 @@ Most reliable but requires soldering skill.
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4. Resolder pin 5
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5. Use firmware to reprogram EEPROM with good C2 image
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### Option D: Wait + Watch (Long Shot)
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### Option D: Wait + Watch (Exhausted — Do Not Use)
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If the boot ROM eventually times out on the I2C read, the device
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will briefly enumerate as bare FX2. This might take several minutes.
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Tested extensively (100+ attempts, 2025-02-19/20) with no success.
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The I2C bus latch does not clear on its own.
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```bash
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# Watch for bare FX2 enumeration
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@ -135,6 +159,24 @@ Once the device enumerates (as bare FX2 or with loaded firmware):
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If you have a backup of the original EEPROM contents, flash that
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instead of the custom firmware.
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## Firmware Fixes Pending Hardware Test
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The custom firmware at `firmware/build/skywalker1.ihx` (15,171 bytes)
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includes three fixes discovered from stock firmware analysis:
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| Commit | Fix | Stock Reference |
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|-----------|------------------------------|--------------------|
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| `e9e5ab8` | Init block readback verify | 0x0DDD readback |
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| `dffef75` | `bcm_wait_ready()` 3-check | 0x2000 pre-write |
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| `0259950` | GPIF stop before boot | 0x1D6A GPIF abort |
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Load immediately after recovery:
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```bash
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python3 tools/fw_load.py load firmware/build/skywalker1.ihx
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```
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Then test: `BOOT_8PSK` (wValue=1), read signal, verify lock.
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## Prevention
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- Never send `BOOT_8PSK (0x89)` with mode 0x84 ("firmware load")
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