Add BOM output, fix LTspice Tier 2 import, real .asc integration tests
- Fix _try_ltspice_generation() to use spicelib.simulators.ltspice_simulator.LTspice instead of the abstract Simulator base class (which always returned unavailable) - Use LTspice.create_netlist() instead of Simulator.run() for correct netlist generation - Add --ltspice-exe CLI option to specify LTspice binary path - Add --bom flag for component BOM CSV output (works on any parse completeness) - Add --bom-wiring flag for wiring BOM CSV from mapped output - Add real 1002A.asc demo circuit and pre-generated .net as test fixtures - Add @pytest.mark.ltspice marker for tests requiring LTspice binary - Bump version to 2026.2.14
This commit is contained in:
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@ -4,7 +4,7 @@ build-backend = "hatchling.build"
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[project]
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name = "spice2wireviz"
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version = "2026.2.13"
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version = "2026.2.14"
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description = "Convert LTspice SPICE netlists to WireViz wiring diagrams"
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authors = [{name = "Ryan Malloy", email = "ryan@supported.systems"}]
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requires-python = ">=3.11"
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@ -52,3 +52,4 @@ select = ["E", "F", "I", "W", "UP", "B", "SIM", "RUF"]
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[tool.pytest.ini_options]
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testpaths = ["tests"]
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markers = ["ltspice: requires LTspice binary installed locally"]
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@ -1,3 +1,3 @@
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"""spice2wireviz — Convert LTspice SPICE netlists to WireViz wiring diagrams."""
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__version__ = "2026.2.13"
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__version__ = "2026.2.14"
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@ -10,6 +10,7 @@ from pathlib import Path
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import click
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from . import __version__
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from .emitter.bom_emitter import emit_component_bom, emit_wiring_bom
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from .emitter.yaml_emitter import emit_yaml
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from .filter import FilterConfig, apply_filters
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from .mapper.inter_module import map_inter_module
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@ -129,6 +130,22 @@ def _parse_comma_list(ctx: click.Context, param: click.Parameter, value: str | N
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is_flag=True,
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help="For .asc files: invoke LTspice to generate a netlist if no companion .net exists.",
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)
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@click.option(
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"--ltspice-exe",
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type=click.Path(path_type=Path),
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default=None,
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help="Path to LTspice binary (for --generate-netlist). Auto-detected if omitted.",
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)
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@click.option(
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"--bom",
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is_flag=True,
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help="Emit component BOM as CSV instead of WireViz YAML.",
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)
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@click.option(
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"--bom-wiring",
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is_flag=True,
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help="Emit wiring BOM as CSV instead of WireViz YAML (requires full mapping).",
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)
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@click.version_option(version=__version__)
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def main(
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input_file: Path,
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@ -152,8 +169,16 @@ def main(
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list_components: bool,
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dry_run: bool,
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generate_netlist: bool,
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ltspice_exe: Path | None,
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bom: bool,
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bom_wiring: bool,
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) -> None:
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"""Convert SPICE netlist to WireViz YAML wiring diagram."""
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# --- Validate mutually exclusive BOM flags ---
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if bom and bom_wiring:
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click.echo("Error: --bom and --bom-wiring are mutually exclusive.", err=True)
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sys.exit(1)
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# --- Parse input (format detection) ---
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is_asc = input_file.suffix.lower() == ".asc"
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completeness = DataCompleteness.FULL # default for .net files
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@ -163,6 +188,7 @@ def main(
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asc_result = parse_asc(
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input_file,
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allow_ltspice_generation=generate_netlist,
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ltspice_exe=str(ltspice_exe) if ltspice_exe else None,
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)
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netlist = asc_result.netlist
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completeness = asc_result.completeness
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@ -234,6 +260,16 @@ def main(
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click.echo(f" {inst.reference} ({inst.subcircuit_name}): {nets}")
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return
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# --- Component BOM (works on any completeness level) ---
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if bom:
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csv_str = emit_component_bom(netlist, filter_config)
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if output:
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output.write_text(csv_str, encoding="utf-8")
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click.echo(f"Wrote component BOM: {output}", err=True)
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else:
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click.echo(csv_str, nl=False)
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return
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# --- Safety gate: block diagram generation on METADATA_ONLY ---
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if completeness == DataCompleteness.METADATA_ONLY:
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click.echo(
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@ -304,6 +340,16 @@ def main(
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else:
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wireviz_dict = map_inter_module(netlist, filter_config, meta)
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# --- Wiring BOM (requires mapping) ---
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if bom_wiring:
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csv_str = emit_wiring_bom(wireviz_dict)
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if output:
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output.write_text(csv_str, encoding="utf-8")
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click.echo(f"Wrote wiring BOM: {output}", err=True)
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else:
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click.echo(csv_str, nl=False)
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return
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# --- Dry run ---
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if dry_run:
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conn_count = len(wireviz_dict.get("connectors", {}))
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109
src/spice2wireviz/emitter/bom_emitter.py
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109
src/spice2wireviz/emitter/bom_emitter.py
Normal file
@ -0,0 +1,109 @@
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"""Bill of Materials CSV output for spice2wireviz.
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Two BOM types:
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- Component BOM: boundary components (connectors, test points) from parsed netlist
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- Wiring BOM: cables and wire connections from mapped WireViz output
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"""
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import csv
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import io
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from typing import Any
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from ..filter import FilterConfig, filter_component, filter_instance
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from ..parser.models import ParsedNetlist
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def emit_component_bom(netlist: ParsedNetlist, config: FilterConfig) -> str:
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"""Generate a CSV bill of materials for boundary components.
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Lists connectors, test points, and subcircuit instances that pass
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the filter configuration. Each row describes one component with its
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reference, prefix, value, pin count, subcircuit scope, and attributes.
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Returns:
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CSV string with header row.
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"""
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buf = io.StringIO()
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writer = csv.writer(buf, lineterminator="\n")
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writer.writerow(["Reference", "Prefix", "Value", "Pins", "Subcircuit", "Attributes"])
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for comp in netlist.top_level_components:
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if not filter_component(comp, config, netlist):
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continue
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attrs = "; ".join(f"{k}={v}" for k, v in sorted(comp.attributes.items()))
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writer.writerow([
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comp.reference,
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comp.prefix,
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comp.value,
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len(comp.pins) or len(comp.nodes),
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comp.subcircuit_scope,
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attrs,
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])
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# Include boundary components inside subcircuit definitions
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for subckt_def in netlist.subcircuit_defs.values():
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for comp in subckt_def.boundary_components:
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if not filter_component(comp, config, netlist):
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continue
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attrs = "; ".join(f"{k}={v}" for k, v in sorted(comp.attributes.items()))
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writer.writerow([
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comp.reference,
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comp.prefix,
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comp.value,
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len(comp.pins) or len(comp.nodes),
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subckt_def.name,
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attrs,
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])
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for inst in netlist.instances:
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if not filter_instance(inst, config, netlist):
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continue
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attrs = "; ".join(f"{k}={v}" for k, v in sorted(inst.attributes.items()))
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writer.writerow([
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inst.reference,
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"X",
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inst.subcircuit_name,
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len(inst.port_to_net),
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"",
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attrs,
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])
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return buf.getvalue()
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def emit_wiring_bom(wireviz_dict: dict[str, Any]) -> str:
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"""Generate a CSV bill of materials for cables/wires from mapped output.
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Each row describes one cable with its name, wire count, net labels,
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and connected endpoints.
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Returns:
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CSV string with header row.
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"""
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buf = io.StringIO()
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writer = csv.writer(buf, lineterminator="\n")
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writer.writerow(["Cable", "Wirecount", "Nets", "From", "To"])
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cables = wireviz_dict.get("cables", {})
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connections = wireviz_dict.get("connections", [])
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# Build cable -> (from_connector, to_connector) mapping from connections
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cable_endpoints: dict[str, tuple[str, str]] = {}
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for conn_set in connections:
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if len(conn_set) < 3:
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continue
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from_name = next(iter(conn_set[0]))
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cable_name = next(iter(conn_set[1]))
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to_name = next(iter(conn_set[2]))
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cable_endpoints[cable_name] = (from_name, to_name)
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for cable_name, cable_def in cables.items():
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wirecount = cable_def.get("wirecount", 0)
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if cable_def.get("colors"):
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wirecount = max(wirecount, len(cable_def["colors"]))
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wirelabels = cable_def.get("wirelabels", [])
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nets = ", ".join(wirelabels) if wirelabels else ""
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from_conn, to_conn = cable_endpoints.get(cable_name, ("", ""))
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writer.writerow([cable_name, wirecount, nets, from_conn, to_conn])
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return buf.getvalue()
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@ -46,6 +46,7 @@ def parse_asc(
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*,
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allow_ltspice_generation: bool = False,
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ltspice_timeout: float = 30.0,
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ltspice_exe: str | Path | None = None,
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) -> AscParseResult:
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"""Parse an LTspice .asc schematic file with tiered netlist resolution.
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@ -58,6 +59,9 @@ def parse_asc(
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allow_ltspice_generation: If True, attempt to invoke LTspice when no
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companion netlist is found. Requires LTspice binary on PATH.
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ltspice_timeout: Timeout in seconds for LTspice netlist generation.
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ltspice_exe: Explicit path to LTspice binary. When provided, calls
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LTspice.create_from() to configure the simulator. When omitted,
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spicelib uses its own auto-detection.
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Returns:
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AscParseResult with the parsed netlist, completeness level, and
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@ -79,7 +83,7 @@ def parse_asc(
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# Tier 2: LTspice generation (opt-in)
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if allow_ltspice_generation:
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result = _try_ltspice_generation(path, ltspice_timeout)
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result = _try_ltspice_generation(path, ltspice_timeout, ltspice_exe)
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if result is not None:
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return result
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@ -109,24 +113,34 @@ def _try_companion_netlist(asc_path: Path) -> AscParseResult | None:
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def _try_ltspice_generation(
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asc_path: Path, timeout: float
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asc_path: Path,
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timeout: float,
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ltspice_exe: str | Path | None = None,
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) -> AscParseResult | None:
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"""Tier 2: Invoke LTspice to generate a netlist from the .asc file."""
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try:
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from spicelib.sim.simulator import Simulator
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from spicelib.simulators.ltspice_simulator import LTspice
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except ImportError:
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return None
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if not Simulator.is_available():
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# Configure the binary path if explicitly provided
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if ltspice_exe is not None:
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exe_path = Path(ltspice_exe)
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if not exe_path.exists():
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print(f"LTspice binary not found: {exe_path}", file=sys.stderr)
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return None
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LTspice.create_from(str(exe_path))
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if not LTspice.is_available():
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print(
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"LTspice binary not found on PATH; skipping netlist generation.",
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"LTspice binary not found; skipping netlist generation. "
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"Use --ltspice-exe to specify the path.",
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file=sys.stderr,
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)
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return None
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net_path = asc_path.with_suffix(".net")
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try:
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Simulator.run(str(asc_path), timeout=timeout)
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net_path = LTspice.create_netlist(str(asc_path), timeout=timeout)
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except TimeoutError as exc:
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print(f"LTspice timed out after {timeout}s: {exc}", file=sys.stderr)
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return None
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@ -140,6 +154,7 @@ def _try_ltspice_generation(
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)
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return None
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net_path = Path(net_path)
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if not net_path.exists():
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print(
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f"LTspice did not produce expected output: {net_path}",
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96
tests/fixtures/1002A.asc
vendored
Normal file
96
tests/fixtures/1002A.asc
vendored
Normal file
@ -0,0 +1,96 @@
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Version 4
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SHEET 1 896 680
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WIRE -256 64 -256 48
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WIRE -128 64 -128 48
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WIRE 288 64 128 64
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WIRE 400 64 368 64
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WIRE 432 64 400 64
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WIRE 544 64 512 64
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WIRE 32 112 16 112
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WIRE 128 112 128 64
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WIRE 128 112 112 112
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WIRE 160 112 128 112
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WIRE 272 112 240 112
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WIRE -256 160 -256 144
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WIRE -128 160 -128 144
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WIRE 192 208 192 192
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WIRE 128 224 128 112
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WIRE 160 224 128 224
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WIRE 448 224 448 208
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WIRE 272 240 272 112
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WIRE 272 240 224 240
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WIRE 304 240 272 240
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WIRE 400 240 400 64
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WIRE 400 240 384 240
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WIRE 416 240 400 240
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WIRE 64 256 -96 256
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WIRE 160 256 64 256
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WIRE 544 256 544 64
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WIRE 544 256 480 256
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WIRE 592 256 544 256
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WIRE -96 272 -96 256
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WIRE 416 272 400 272
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WIRE 192 288 192 272
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WIRE 448 304 448 288
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WIRE -96 384 -96 352
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WIRE 160 384 -96 384
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WIRE 400 384 400 272
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WIRE 400 384 160 384
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WIRE -96 400 -96 384
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WIRE -96 496 -96 480
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FLAG -128 160 0
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FLAG 192 192 +V
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FLAG -128 48 +V
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FLAG 192 288 -V
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FLAG -256 160 0
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FLAG -256 48 -V
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FLAG 16 112 0
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FLAG -96 496 0
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FLAG 448 208 +V
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FLAG 448 304 -V
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FLAG 64 256 IN-
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FLAG 160 384 IN+
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FLAG 592 256 OUT
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SYMBOL voltage -128 48 R0
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SYMATTR InstName V1
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SYMATTR Value 15
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SYMBOL voltage -256 48 R0
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SYMATTR InstName V2
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SYMATTR Value -15
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SYMBOL res 256 96 R90
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WINDOW 0 0 56 VBottom 2
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WINDOW 3 32 56 VTop 2
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SYMATTR InstName R1
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SYMATTR Value 10K
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SYMBOL res 128 96 R90
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WINDOW 0 0 56 VBottom 2
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WINDOW 3 32 56 VTop 2
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SYMATTR InstName R2
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SYMATTR Value 100K
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SYMBOL voltage -96 256 R0
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SYMATTR InstName V3
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SYMATTR Value SINE(0 1m 100)
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SYMBOL res 384 48 R90
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WINDOW 0 0 56 VBottom 2
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WINDOW 3 32 56 VTop 2
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SYMATTR InstName R3
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SYMATTR Value 2.2K
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SYMBOL res 400 224 R90
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WINDOW 0 0 56 VBottom 2
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WINDOW 3 32 56 VTop 2
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SYMATTR InstName R4
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SYMATTR Value 10K
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SYMBOL res 528 48 R90
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WINDOW 0 0 56 VBottom 2
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WINDOW 3 32 56 VTop 2
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SYMATTR InstName R5
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SYMATTR Value 100K
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SYMBOL voltage -96 384 R0
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SYMATTR InstName V4
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SYMATTR Value SINE(0 1 10)
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SYMBOL opamps\\LT1002A 192 176 R0
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SYMATTR InstName U1
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SYMBOL opamps\\LT1002A 448 192 R0
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SYMATTR InstName U2
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TEXT 440 392 Left 2 !.tran 300m
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TEXT -48 -16 Left 2 ;Two Op Amp Instrumentation Amplifier
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19
tests/fixtures/1002A.net
vendored
Normal file
19
tests/fixtures/1002A.net
vendored
Normal file
@ -0,0 +1,19 @@
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* Z:\tmp\1002A.asc
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* Generated by LTspice 26.0.1 for Windows.
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V1 +V 0 15
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V2 -V 0 -15
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R1 N003 N001 10K
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R2 N001 0 100K
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V3 IN- IN+ SINE(0 1m 100)
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R3 N002 N001 2.2K
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R4 N002 N003 10K
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R5 OUT N002 100K
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V4 IN+ 0 SINE(0 1 10)
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X§U1 IN- N001 +V -V N003 LT1001 ;§pnba In+)In-)V+)V-)OUT
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X§U2 IN+ N002 +V -V OUT LT1001 ;§pnba In+)In-)V+)V-)OUT
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.tran 300m
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* Two Op Amp Instrumentation Amplifier
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* Library below included based on ModelFile attribute of instance X§U1, X§U2 (C:\users\rpm\AppData\Local\LTspice\lib\sym\OpAmps\LT1002A.asy)
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.lib LTC.lib
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.backanno
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.end
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@ -206,8 +206,7 @@ class TestLTspiceGeneration:
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result = parse_asc(asc)
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assert result.completeness == DataCompleteness.METADATA_ONLY
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@patch("spice2wireviz.parser.asc.Simulator", create=True)
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def test_ltspice_generation_success(self, mock_sim_cls, tmp_path):
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def test_ltspice_generation_success(self, tmp_path):
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"""Mocked LTspice successfully generates a .net file."""
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asc = tmp_path / "test.asc"
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asc.write_text("Version 4\nSHEET 1 880 680\n")
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@ -220,7 +219,7 @@ class TestLTspiceGeneration:
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".ends gen_mod\n"
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)
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# Mock the import path inside _try_ltspice_generation
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# Mock the whole Tier 2 function
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with patch(
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"spice2wireviz.parser.asc._try_ltspice_generation"
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) as mock_tier2:
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@ -279,3 +278,89 @@ class TestCompanionNetlistInternalHelper:
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assert result is not None
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assert result.completeness == DataCompleteness.FULL
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assert result.source_net == net
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class TestRealAscIntegration:
|
||||
"""Integration tests with a real LTspice-generated .asc / .net pair.
|
||||
|
||||
1002A.asc is a two op-amp instrumentation amplifier from the LTspice
|
||||
demo circuit archive. The companion 1002A.net was pre-generated by
|
||||
LTspice so these tests work in CI without LTspice installed.
|
||||
"""
|
||||
|
||||
def test_real_asc_companion_resolution(self):
|
||||
"""Tier 1: 1002A.asc resolves to companion 1002A.net."""
|
||||
result = parse_asc(FIXTURES / "1002A.asc")
|
||||
assert result.completeness == DataCompleteness.FULL
|
||||
assert result.source_net is not None
|
||||
assert result.source_net.name == "1002A.net"
|
||||
|
||||
def test_real_asc_has_components(self):
|
||||
"""The parsed netlist has X* instances (op-amps)."""
|
||||
result = parse_asc(FIXTURES / "1002A.asc")
|
||||
netlist = result.netlist
|
||||
# 1002A.net has X§U1 and X§U2 (LTspice op-amp instances)
|
||||
x_refs = [inst.reference for inst in netlist.instances]
|
||||
assert len(x_refs) >= 2
|
||||
# The § character is part of LTspice's hierarchical naming
|
||||
assert any("U1" in ref for ref in x_refs)
|
||||
assert any("U2" in ref for ref in x_refs)
|
||||
|
||||
def test_real_asc_has_nets(self):
|
||||
"""The parsed netlist has known nets from the circuit."""
|
||||
result = parse_asc(FIXTURES / "1002A.asc")
|
||||
netlist = result.netlist
|
||||
assert len(netlist.all_nets) > 0
|
||||
# The circuit uses +V, -V, OUT, IN+, IN- as net names
|
||||
net_names = {n.upper() for n in netlist.all_nets}
|
||||
assert "+V" in net_names or "V+" in net_names or any("V" in n for n in net_names)
|
||||
|
||||
def test_real_asc_no_warnings_on_companion(self):
|
||||
"""Companion resolution should produce no warnings."""
|
||||
result = parse_asc(FIXTURES / "1002A.asc")
|
||||
# Warnings are acceptable for enrichment, but not for core parsing
|
||||
# Only check that we didn't get "no companion" warnings
|
||||
for w in result.warnings:
|
||||
assert "no companion" not in w.lower()
|
||||
|
||||
@pytest.mark.ltspice
|
||||
def test_real_asc_ltspice_generation(self, tmp_path):
|
||||
"""Tier 2: generate .net from .asc using LTspice binary.
|
||||
|
||||
Requires LTspice installed. Skipped in CI.
|
||||
"""
|
||||
import shutil
|
||||
|
||||
ltspice_path = Path("/home/rpm/.local/bin/ltspice")
|
||||
if not ltspice_path.exists():
|
||||
pytest.skip("LTspice binary not found")
|
||||
|
||||
# Copy .asc to temp dir (avoid polluting fixtures)
|
||||
asc_copy = tmp_path / "1002A.asc"
|
||||
shutil.copy2(FIXTURES / "1002A.asc", asc_copy)
|
||||
|
||||
# Remove any existing .net so Tier 2 is forced
|
||||
net_copy = tmp_path / "1002A.net"
|
||||
if net_copy.exists():
|
||||
net_copy.unlink()
|
||||
|
||||
result = parse_asc(
|
||||
asc_copy,
|
||||
allow_ltspice_generation=True,
|
||||
ltspice_exe=str(ltspice_path),
|
||||
)
|
||||
assert result.completeness == DataCompleteness.FULL
|
||||
assert result.source_net is not None
|
||||
assert result.source_net.name == "1002A.net"
|
||||
|
||||
def test_ltspice_exe_nonexistent_path(self, tmp_path):
|
||||
"""--ltspice-exe with a bad path falls through to Tier 3."""
|
||||
asc = tmp_path / "test.asc"
|
||||
asc.write_text("Version 4\nSHEET 1 880 680\n")
|
||||
|
||||
result = parse_asc(
|
||||
asc,
|
||||
allow_ltspice_generation=True,
|
||||
ltspice_exe="/nonexistent/ltspice",
|
||||
)
|
||||
assert result.completeness == DataCompleteness.METADATA_ONLY
|
||||
|
||||
222
tests/test_bom_emitter.py
Normal file
222
tests/test_bom_emitter.py
Normal file
@ -0,0 +1,222 @@
|
||||
"""Tests for the BOM CSV emitter."""
|
||||
|
||||
import csv
|
||||
import io
|
||||
from pathlib import Path
|
||||
|
||||
from click.testing import CliRunner
|
||||
|
||||
from spice2wireviz.cli import main
|
||||
from spice2wireviz.emitter.bom_emitter import emit_component_bom, emit_wiring_bom
|
||||
from spice2wireviz.filter import FilterConfig
|
||||
from spice2wireviz.mapper.inter_module import map_inter_module
|
||||
from spice2wireviz.parser.models import (
|
||||
ParsedNetlist,
|
||||
SpiceComponent,
|
||||
SpicePin,
|
||||
)
|
||||
from spice2wireviz.parser.netlist import parse_netlist
|
||||
|
||||
FIXTURES = Path(__file__).parent / "fixtures"
|
||||
|
||||
|
||||
def _parse_csv(csv_str: str) -> list[dict[str, str]]:
|
||||
"""Parse a CSV string into a list of dicts."""
|
||||
reader = csv.DictReader(io.StringIO(csv_str))
|
||||
return list(reader)
|
||||
|
||||
|
||||
class TestComponentBom:
|
||||
def test_simple_board_bom(self):
|
||||
"""Component BOM from simple_board.net has expected connectors."""
|
||||
netlist = parse_netlist(FIXTURES / "simple_board.net")
|
||||
config = FilterConfig()
|
||||
csv_str = emit_component_bom(netlist, config)
|
||||
|
||||
rows = _parse_csv(csv_str)
|
||||
assert len(rows) > 0
|
||||
|
||||
# Check CSV is parseable and has expected columns
|
||||
assert "Reference" in rows[0]
|
||||
assert "Prefix" in rows[0]
|
||||
assert "Value" in rows[0]
|
||||
|
||||
def test_bom_respects_filters(self):
|
||||
"""Filter config limits which components appear in BOM."""
|
||||
netlist = parse_netlist(FIXTURES / "multi_board.net")
|
||||
# Only include J-prefix components
|
||||
config = FilterConfig(include_prefixes=["J"])
|
||||
csv_str = emit_component_bom(netlist, config)
|
||||
|
||||
rows = _parse_csv(csv_str)
|
||||
for row in rows:
|
||||
assert row["Prefix"] == "J"
|
||||
|
||||
def test_bom_includes_subcircuit_boundary_components(self):
|
||||
"""Components inside .subckt definitions are included."""
|
||||
netlist = parse_netlist(FIXTURES / "simple_board.net")
|
||||
config = FilterConfig()
|
||||
csv_str = emit_component_bom(netlist, config)
|
||||
|
||||
rows = _parse_csv(csv_str)
|
||||
subcircuit_refs = [r for r in rows if r["Subcircuit"]]
|
||||
assert len(subcircuit_refs) > 0
|
||||
|
||||
def test_bom_includes_instances(self):
|
||||
"""X* instances appear in BOM with subcircuit name as value."""
|
||||
netlist = parse_netlist(FIXTURES / "multi_board.net")
|
||||
config = FilterConfig()
|
||||
csv_str = emit_component_bom(netlist, config)
|
||||
|
||||
rows = _parse_csv(csv_str)
|
||||
x_rows = [r for r in rows if r["Prefix"] == "X"]
|
||||
assert len(x_rows) > 0
|
||||
# Value column should contain the subcircuit name
|
||||
for row in x_rows:
|
||||
assert row["Value"] # not empty
|
||||
|
||||
def test_empty_netlist_produces_header_only(self):
|
||||
"""An empty netlist produces CSV with just the header."""
|
||||
netlist = ParsedNetlist()
|
||||
config = FilterConfig()
|
||||
csv_str = emit_component_bom(netlist, config)
|
||||
|
||||
rows = _parse_csv(csv_str)
|
||||
assert len(rows) == 0
|
||||
|
||||
# But header should exist
|
||||
lines = csv_str.strip().split("\n")
|
||||
assert len(lines) == 1
|
||||
assert "Reference" in lines[0]
|
||||
|
||||
def test_bom_preserves_attributes(self):
|
||||
"""Component attributes appear in the Attributes column."""
|
||||
netlist = ParsedNetlist(
|
||||
top_level_components=[
|
||||
SpiceComponent(
|
||||
reference="J1", prefix="J", value="DB9", nodes=["A", "B"],
|
||||
pins=[
|
||||
SpicePin(name="A", index=1, net_name="A"),
|
||||
SpicePin(name="B", index=2, net_name="B"),
|
||||
],
|
||||
attributes={"Footprint": "DSUB-9", "MPN": "DE-9S"},
|
||||
),
|
||||
],
|
||||
)
|
||||
config = FilterConfig()
|
||||
csv_str = emit_component_bom(netlist, config)
|
||||
|
||||
rows = _parse_csv(csv_str)
|
||||
assert len(rows) == 1
|
||||
assert "Footprint=DSUB-9" in rows[0]["Attributes"]
|
||||
assert "MPN=DE-9S" in rows[0]["Attributes"]
|
||||
|
||||
|
||||
class TestWiringBom:
|
||||
def test_multi_board_wiring_bom(self):
|
||||
"""Wiring BOM from mapped multi_board.net has cables."""
|
||||
netlist = parse_netlist(FIXTURES / "multi_board.net")
|
||||
config = FilterConfig()
|
||||
wireviz_dict = map_inter_module(netlist, config)
|
||||
csv_str = emit_wiring_bom(wireviz_dict)
|
||||
|
||||
rows = _parse_csv(csv_str)
|
||||
assert len(rows) > 0
|
||||
assert "Cable" in rows[0]
|
||||
assert "Wirecount" in rows[0]
|
||||
assert "From" in rows[0]
|
||||
assert "To" in rows[0]
|
||||
|
||||
def test_wiring_bom_has_net_labels(self):
|
||||
"""Cables include net name labels."""
|
||||
netlist = parse_netlist(FIXTURES / "multi_board.net")
|
||||
config = FilterConfig()
|
||||
wireviz_dict = map_inter_module(netlist, config)
|
||||
csv_str = emit_wiring_bom(wireviz_dict)
|
||||
|
||||
rows = _parse_csv(csv_str)
|
||||
# At least some cables should have net labels
|
||||
nets_found = [r for r in rows if r["Nets"]]
|
||||
assert len(nets_found) > 0
|
||||
|
||||
def test_wiring_bom_endpoints(self):
|
||||
"""Each cable connects two endpoints."""
|
||||
netlist = parse_netlist(FIXTURES / "multi_board.net")
|
||||
config = FilterConfig()
|
||||
wireviz_dict = map_inter_module(netlist, config)
|
||||
csv_str = emit_wiring_bom(wireviz_dict)
|
||||
|
||||
rows = _parse_csv(csv_str)
|
||||
for row in rows:
|
||||
assert row["From"] # not empty
|
||||
assert row["To"] # not empty
|
||||
|
||||
def test_empty_wireviz_produces_header_only(self):
|
||||
"""An empty wireviz dict produces CSV with just the header."""
|
||||
csv_str = emit_wiring_bom({})
|
||||
|
||||
rows = _parse_csv(csv_str)
|
||||
assert len(rows) == 0
|
||||
|
||||
lines = csv_str.strip().split("\n")
|
||||
assert len(lines) == 1
|
||||
assert "Cable" in lines[0]
|
||||
|
||||
|
||||
class TestBomCli:
|
||||
"""CLI integration for --bom and --bom-wiring flags."""
|
||||
|
||||
def test_bom_flag(self):
|
||||
"""--bom produces CSV output."""
|
||||
runner = CliRunner()
|
||||
result = runner.invoke(
|
||||
main, [str(FIXTURES / "simple_board.net"), "--bom"]
|
||||
)
|
||||
assert result.exit_code == 0
|
||||
assert "Reference" in result.output
|
||||
# Should be CSV, not YAML
|
||||
assert "connectors:" not in result.output
|
||||
|
||||
def test_bom_wiring_flag(self):
|
||||
"""--bom-wiring produces cable CSV."""
|
||||
runner = CliRunner()
|
||||
result = runner.invoke(
|
||||
main,
|
||||
[str(FIXTURES / "multi_board.net"), "--bom-wiring"],
|
||||
)
|
||||
assert result.exit_code == 0
|
||||
assert "Cable" in result.output
|
||||
assert "Wirecount" in result.output
|
||||
# Should be CSV, not YAML
|
||||
assert "connectors:" not in result.output
|
||||
|
||||
def test_bom_wiring_with_subcircuit(self):
|
||||
"""--bom-wiring with -s uses single-module mapping."""
|
||||
runner = CliRunner()
|
||||
result = runner.invoke(
|
||||
main,
|
||||
[str(FIXTURES / "simple_board.net"), "-s", "amplifier_board", "--bom-wiring"],
|
||||
)
|
||||
assert result.exit_code == 0
|
||||
assert "Cable" in result.output
|
||||
|
||||
def test_bom_and_bom_wiring_mutually_exclusive(self):
|
||||
"""--bom and --bom-wiring cannot be used together."""
|
||||
runner = CliRunner()
|
||||
result = runner.invoke(
|
||||
main,
|
||||
[str(FIXTURES / "simple_board.net"), "--bom", "--bom-wiring"],
|
||||
)
|
||||
assert result.exit_code != 0
|
||||
|
||||
def test_bom_to_file(self, tmp_path):
|
||||
"""--bom with -o writes to file."""
|
||||
out = tmp_path / "bom.csv"
|
||||
runner = CliRunner()
|
||||
result = runner.invoke(
|
||||
main, [str(FIXTURES / "simple_board.net"), "--bom", "-o", str(out)]
|
||||
)
|
||||
assert result.exit_code == 0
|
||||
assert out.exists()
|
||||
content = out.read_text()
|
||||
assert "Reference" in content
|
||||
@ -14,7 +14,7 @@ class TestCLIBasic:
|
||||
runner = CliRunner()
|
||||
result = runner.invoke(main, ["--version"])
|
||||
assert result.exit_code == 0
|
||||
assert "2026.2.13" in result.output
|
||||
assert "2026.2.14" in result.output
|
||||
|
||||
def test_list_subcircuits(self):
|
||||
runner = CliRunner()
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user