Add star-topology layout optimization for single-module diagrams
Three-pass optimization eliminates cable crossings: 1. Order boundary components by average header pin position 2. Regroup header pins by boundary component (reduces inter-cable crossings) 3. Reorder boundary component pins to parallel header (eliminates within-cable crossings) Safety hardening from Apollo review: - Duplicate header pin deduplication (prevents silent mapping corruption) - Connection structure validation at entry - Fan-out averaging for component pins connected to multiple header pins - Explicit ValueError on pin remapping failures with diagnostic context 145 tests passing (was 130).
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@ -20,8 +20,8 @@ connectors:
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J2:
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type: SIG_CONN
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pinlabels:
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- SIGNAL_IN
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- VOUT
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- SIGNAL_IN
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notes: 'SPICE ref: J2, nets: SIGNAL_IN, VOUT'
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TP1:
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type: TP
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@ -63,5 +63,5 @@ connections:
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- 1
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- 2
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- J2:
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- 2
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- 1
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- 2
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@ -8,11 +8,18 @@ defined inside it) and port interface. Generates:
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- Cables connecting the module header to boundary components via shared nets
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This shows the external interface of a single board/module.
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Layout optimization for the star topology:
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1. Order boundary components by average header pin position
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2. Group header pins by boundary component (reduces inter-cable crossings)
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3. Reorder boundary component pins to be parallel with header (eliminates
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within-cable crossings)
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"""
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from __future__ import annotations
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import sys
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from collections import defaultdict
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from typing import Any
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from ..emitter.yaml_emitter import (
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@ -34,6 +41,257 @@ def _net_wire_color(net: str, netlist: ParsedNetlist) -> str:
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return ""
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# ---------------------------------------------------------------------------
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# Layout optimization helpers
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# ---------------------------------------------------------------------------
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def _remap_pins(
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name: str, pins: int | list[int], mapping: dict[int, int]
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) -> int | list[int]:
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"""Apply pin index remapping, failing explicitly if a pin is missing."""
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try:
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if isinstance(pins, int):
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return mapping[pins]
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return [mapping[p] for p in pins]
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except KeyError as e:
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raise ValueError(
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f"Pin remapping failed for {name}: pin {e.args[0]} not in "
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f"mapping. Available: {sorted(mapping.keys())}, "
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f"Requested: {pins if isinstance(pins, int) else list(pins)}"
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) from e
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def _optimize_single_layout(
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header_name: str,
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connectors: dict[str, dict[str, Any]],
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cables: dict[str, dict[str, Any]],
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connections: list[list[dict[str, Any]]],
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) -> tuple[
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dict[str, dict[str, Any]],
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dict[str, dict[str, Any]],
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list[list[dict[str, Any]]],
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]:
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"""Optimize star-topology layout for single-module diagrams.
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Three-pass optimization:
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1. Order boundary components by average header pin position
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2. Regroup header pins so pins connecting to the same boundary
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component are adjacent (reduces inter-cable crossings)
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3. Reorder boundary component pins to be parallel with header
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(eliminates within-cable crossings)
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"""
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if len(connectors) < 2 or not connections:
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return connectors, cables, connections
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header = connectors.get(header_name)
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if not header or "pinlabels" not in header:
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return connectors, cables, connections
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header_labels = header["pinlabels"]
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n_header = len(header_labels)
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# --- Parse connections to extract (header_pin, comp_pin) pairs ---
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comp_pin_pairs: dict[str, list[tuple[int, int]]] = defaultdict(list)
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for i, conn in enumerate(connections):
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if len(conn) < 3:
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raise ValueError(
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f"Connection {i} has {len(conn)} elements, expected at least 3 "
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f"(connector, cable, connector): {conn}"
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)
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left_name = next(iter(conn[0]))
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right_name = next(iter(conn[2]))
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if left_name == header_name:
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comp_name = right_name
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h_pins = conn[0][header_name]
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c_pins = conn[2][comp_name]
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elif right_name == header_name:
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comp_name = left_name
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h_pins = conn[2][header_name]
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c_pins = conn[0][comp_name]
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else:
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continue
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h_list = [h_pins] if isinstance(h_pins, int) else list(h_pins)
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c_list = [c_pins] if isinstance(c_pins, int) else list(c_pins)
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for h, c in zip(h_list, c_list, strict=True):
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comp_pin_pairs[comp_name].append((h, c))
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if not comp_pin_pairs:
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return connectors, cables, connections
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# --- Step 1: Order boundary components by average header pin ---
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comp_avg: dict[str, float] = {}
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for comp_name, pairs in comp_pin_pairs.items():
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comp_avg[comp_name] = sum(h for h, _ in pairs) / len(pairs)
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boundary_order = sorted(comp_avg.keys(), key=lambda c: (comp_avg[c], c))
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# --- Step 2: Regroup header pins by boundary component ---
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# Pins connecting to the first boundary component come first, then
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# the second, etc. Unconnected header pins go at the end.
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# Duplicate detection: a header pin shared by multiple boundary
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# components (e.g., GND routed to both J1 and J2) is assigned to
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# the first component in boundary_order — subsequent duplicates
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# are skipped to avoid corrupting the pin mapping.
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new_header_order: list[int] = []
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seen_pins: set[int] = set()
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for comp_name in boundary_order:
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comp_h_pins = sorted(h for h, _ in comp_pin_pairs[comp_name])
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for pin in comp_h_pins:
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if pin not in seen_pins:
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seen_pins.add(pin)
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new_header_order.append(pin)
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connected = set(new_header_order)
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for p in range(1, n_header + 1):
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if p not in connected:
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new_header_order.append(p)
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# Build header pin mapping (old position -> new position)
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header_mapping: dict[int, int] | None = None
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if new_header_order != list(range(1, n_header + 1)):
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header_mapping = {
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old: new for new, old in enumerate(new_header_order, 1)
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}
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new_header_labels = [header_labels[old - 1] for old in new_header_order]
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else:
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new_header_labels = header_labels
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# --- Step 3: Reorder boundary component pins to parallel header ---
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# For each component, sort its pins by the corresponding (remapped)
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# header pin position so wires run parallel without crossing.
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comp_mappings: dict[str, dict[int, int]] = {}
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for comp_name, pairs in comp_pin_pairs.items():
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comp_conn = connectors.get(comp_name, {})
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comp_labels = comp_conn.get("pinlabels", [])
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n_comp = len(comp_labels) if comp_labels else comp_conn.get("pincount", 0)
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if n_comp <= 1:
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continue
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# Map each component pin to its effective header position.
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# A pin may connect to multiple header pins (fan-out); use
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# the average position rather than last-wins.
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comp_pin_h_positions: dict[int, list[float]] = defaultdict(list)
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for h, c in pairs:
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h_pos = header_mapping[h] if header_mapping else h
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comp_pin_h_positions[c].append(float(h_pos))
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comp_pin_to_h_pos: dict[int, float] = {
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pin: sum(positions) / len(positions)
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for pin, positions in comp_pin_h_positions.items()
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}
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# Sort: connected pins by header position, unconnected at end
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all_comp_pins = list(range(1, n_comp + 1))
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sorted_comp = sorted(
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all_comp_pins,
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key=lambda p: (comp_pin_to_h_pos.get(p, float("inf")), p),
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)
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if sorted_comp != all_comp_pins:
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mapping = {old: new for new, old in enumerate(sorted_comp, 1)}
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comp_mappings[comp_name] = mapping
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# --- Build new ordered connectors dict (no in-place mutation) ---
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ordered: dict[str, dict[str, Any]] = {}
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# Header first (with possible pinlabel update)
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if header_mapping:
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new_h: dict[str, Any] = {}
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for k, v in header.items():
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new_h[k] = new_header_labels if k == "pinlabels" else v
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ordered[header_name] = new_h
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else:
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ordered[header_name] = connectors[header_name]
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# Boundary components in order (with possible pinlabel update)
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for comp_name in boundary_order:
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if comp_name not in connectors:
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continue
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comp_conn = connectors[comp_name]
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if comp_name in comp_mappings:
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mapping = comp_mappings[comp_name]
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comp_labels = comp_conn.get("pinlabels", [])
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if comp_labels:
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sorted_pins = sorted(mapping.keys(), key=lambda p: mapping[p])
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new_labels = [comp_labels[old - 1] for old in sorted_pins]
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new_comp: dict[str, Any] = {}
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for k, v in comp_conn.items():
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new_comp[k] = new_labels if k == "pinlabels" else v
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ordered[comp_name] = new_comp
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else:
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ordered[comp_name] = comp_conn
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else:
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ordered[comp_name] = comp_conn
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# Remaining connectors (e.g., disconnected test points)
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for name, conn in connectors.items():
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if name not in ordered:
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ordered[name] = conn
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# --- Apply all pin mappings to connections ---
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all_mappings: dict[str, dict[int, int]] = {}
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if header_mapping:
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all_mappings[header_name] = header_mapping
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all_mappings.update(comp_mappings)
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if all_mappings:
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updated: list[list[dict[str, Any]]] = []
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for conn in connections:
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# Shallow copy: only conn[0] and conn[2] are replaced (new dicts).
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# conn[1] (cable) is shared by reference — safe because cables
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# are not remapped in this pass.
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new_conn = list(conn)
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left_name = next(iter(conn[0]))
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if left_name in all_mappings:
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new_conn[0] = {
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left_name: _remap_pins(
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left_name, conn[0][left_name], all_mappings[left_name]
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)
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}
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right_name = next(iter(conn[2]))
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if right_name in all_mappings:
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new_conn[2] = {
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right_name: _remap_pins(
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right_name, conn[2][right_name], all_mappings[right_name]
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)
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}
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updated.append(new_conn)
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connections = updated
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# --- Sort connections by minimum header pin (top-to-bottom order) ---
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def _sort_key(conn: list[dict[str, Any]]) -> tuple[float, ...]:
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left_name = next(iter(conn[0]))
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right_name = next(iter(conn[2]))
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if left_name == header_name:
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h_pins = conn[0][header_name]
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elif right_name == header_name:
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h_pins = conn[2][header_name]
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else:
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return (float("inf"),)
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pin_list = [h_pins] if isinstance(h_pins, int) else h_pins
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return (min(pin_list),)
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connections.sort(key=_sort_key)
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return ordered, cables, connections
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# ---------------------------------------------------------------------------
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# Main mapper
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# ---------------------------------------------------------------------------
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def map_single_module(
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netlist: ParsedNetlist,
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subcircuit_name: str,
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@ -143,6 +401,11 @@ def map_single_module(
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comp_name, mapped_comp,
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))
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# --- Optimize layout for cleaner diagrams ---
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connectors, cables, connections = _optimize_single_layout(
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header_name, connectors, cables, connections
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)
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return assemble_wireviz_doc(connectors, cables, connections, metadata)
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@ -5,7 +5,11 @@ from pathlib import Path
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import pytest
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from spice2wireviz.filter import FilterConfig
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from spice2wireviz.mapper.single_module import map_single_module
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from spice2wireviz.mapper.single_module import (
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_optimize_single_layout,
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_remap_pins,
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map_single_module,
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)
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from spice2wireviz.parser.netlist import parse_netlist
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FIXTURES = Path(__file__).parent / "fixtures"
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@ -102,3 +106,215 @@ class TestSingleModuleFiltering:
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result = map_single_module(netlist, "amplifier_board", config)
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assert "TP1" not in result["connectors"]
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class TestSingleModuleLayoutOptimization:
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"""Tests for the star-topology layout optimization."""
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def test_boundary_component_order(self):
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"""Boundary components should appear in header pin order."""
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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names = list(result["connectors"].keys())
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# Header first, then J1 (avg pin 1.5), then J2 (avg pin 3.5), then TP1
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assert names[0] == "amplifier_board"
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assert names.index("J1") < names.index("J2")
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def test_j2_pins_reordered_to_eliminate_crossing(self):
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"""J2 pins should be [VOUT, SIGNAL_IN] to match header order."""
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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j2 = result["connectors"]["J2"]
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# Header has VOUT@3, SIGNAL_IN@4 — J2 must match: VOUT first
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assert j2["pinlabels"] == ["VOUT", "SIGNAL_IN"]
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def test_connections_parallel_after_optimization(self):
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"""After optimization, cable wires should not cross (pins monotonic)."""
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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for conn in result["connections"]:
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left_pins = conn[0][next(iter(conn[0]))]
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right_pins = conn[2][next(iter(conn[2]))]
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l_list = [left_pins] if isinstance(left_pins, int) else left_pins
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r_list = [right_pins] if isinstance(right_pins, int) else right_pins
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assert l_list == sorted(l_list), f"Left pins not sorted: {l_list}"
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assert r_list == sorted(r_list), f"Right pins not sorted: {r_list}"
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def test_connection_pins_valid(self):
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"""All pin indices must be within the connector's pin count."""
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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result = map_single_module(netlist, "amplifier_board")
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connectors = result["connectors"]
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for conn in result["connections"]:
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for entry in [conn[0], conn[2]]:
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name = next(iter(entry))
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pins = entry[name]
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pin_list = [pins] if isinstance(pins, int) else pins
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n_pins = len(connectors[name].get("pinlabels", []))
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if n_pins == 0:
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n_pins = connectors[name].get("pincount", 0)
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for p in pin_list:
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assert 1 <= p <= n_pins, (
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f"Pin {p} out of range for {name} ({n_pins} pins)"
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)
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def test_optimize_no_crash_single_connector(self):
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"""Single connector (no boundary) should pass through."""
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connectors = {"header": {"pinlabels": ["A", "B"]}}
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result_c, _cb, _cn = _optimize_single_layout("header", connectors, {}, [])
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assert result_c == connectors
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def test_optimize_no_crash_empty(self):
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"""Empty inputs should pass through."""
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result_c, _cb, _cn = _optimize_single_layout("header", {}, {}, [])
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assert result_c == {}
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def test_header_pin_regrouping(self):
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"""Header pins connecting to the same component should be grouped."""
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# Synthetic: header has interleaved pins
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# Pin 1 → compA, Pin 2 → compB, Pin 3 → compA, Pin 4 → compB
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connectors = {
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"H": {"pinlabels": ["A1", "B1", "A2", "B2"]},
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"CA": {"pinlabels": ["X", "Y"]},
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"CB": {"pinlabels": ["M", "N"]},
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}
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connections = [
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[{"H": [1, 3]}, {"W1": [1, 2]}, {"CA": [1, 2]}],
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[{"H": [2, 4]}, {"W2": [1, 2]}, {"CB": [1, 2]}],
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]
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result_c, _, result_cn = _optimize_single_layout(
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"H", connectors, {}, connections
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)
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# Header should be regrouped: [A1, A2, B1, B2]
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assert result_c["H"]["pinlabels"] == ["A1", "A2", "B1", "B2"]
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# CA should come before CB
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names = list(result_c.keys())
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assert names.index("CA") < names.index("CB")
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def test_header_regrouping_updates_connections(self):
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"""After header regrouping, connection pin indices must be updated."""
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connectors = {
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"H": {"pinlabels": ["A1", "B1", "A2", "B2"]},
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"CA": {"pinlabels": ["X", "Y"]},
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"CB": {"pinlabels": ["M", "N"]},
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}
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connections = [
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[{"H": [1, 3]}, {"W1": [1, 2]}, {"CA": [1, 2]}],
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[{"H": [2, 4]}, {"W2": [1, 2]}, {"CB": [1, 2]}],
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]
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_, _, result_cn = _optimize_single_layout("H", connectors, {}, connections)
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# After regrouping: H pins [A1,A2,B1,B2] → old 1→new 1, old 3→new 2,
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# old 2→new 3, old 4→new 4
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# Connection 1: H:[1,3] should become H:[1,2]
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h_pins_0 = result_cn[0][0]["H"]
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assert h_pins_0 == [1, 2]
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# Connection 2: H:[2,4] should become H:[3,4]
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h_pins_1 = result_cn[1][0]["H"]
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assert h_pins_1 == [3, 4]
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def test_comp_pin_reorder_eliminates_crossing(self):
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"""Component pins should be reordered to match header pin order."""
|
||||
# Header: [A, B], CompX: [Y, X] where A→Y and B→X
|
||||
# This means header pin 1→comp pin 2, header pin 2→comp pin 1 (crossing!)
|
||||
connectors = {
|
||||
"H": {"pinlabels": ["A", "B"]},
|
||||
"CX": {"pinlabels": ["Y", "X"]},
|
||||
}
|
||||
connections = [
|
||||
[{"H": [1, 2]}, {"W1": [1, 2]}, {"CX": [2, 1]}],
|
||||
]
|
||||
result_c, _, result_cn = _optimize_single_layout(
|
||||
"H", connectors, {}, connections
|
||||
)
|
||||
# CX should be reordered to [X, Y] so pin 1→pin 1, pin 2→pin 2
|
||||
assert result_c["CX"]["pinlabels"] == ["X", "Y"]
|
||||
# Connection should now be CX:[1,2] (no crossing)
|
||||
assert result_cn[0][2]["CX"] == [1, 2]
|
||||
|
||||
def test_disconnected_test_point_preserved(self):
|
||||
"""Test points with no header connection should appear last."""
|
||||
netlist = parse_netlist(FIXTURES / "simple_board.net")
|
||||
result = map_single_module(netlist, "amplifier_board")
|
||||
|
||||
names = list(result["connectors"].keys())
|
||||
# TP1 connects to internal net N001 (not a port), so it's disconnected
|
||||
# from the header. It should appear after connected components.
|
||||
assert names[-1] == "TP1"
|
||||
|
||||
def test_connections_sorted_by_header_pin(self):
|
||||
"""Connections should be sorted by their minimum header pin."""
|
||||
netlist = parse_netlist(FIXTURES / "simple_board.net")
|
||||
result = map_single_module(netlist, "amplifier_board")
|
||||
|
||||
prev_min = 0
|
||||
for conn in result["connections"]:
|
||||
# Header is always on the left in single-module connections
|
||||
left_name = next(iter(conn[0]))
|
||||
h_pins = conn[0][left_name]
|
||||
pin_list = [h_pins] if isinstance(h_pins, int) else h_pins
|
||||
min_pin = min(pin_list)
|
||||
assert min_pin >= prev_min, (
|
||||
f"Connection order wrong: min pin {min_pin} < previous {prev_min}"
|
||||
)
|
||||
prev_min = min_pin
|
||||
|
||||
def test_shared_header_pin_deduplication(self):
|
||||
"""Header pin shared by two components should not corrupt mapping."""
|
||||
# Pin 2 of header connects to both CA and CB (e.g., GND fan-out)
|
||||
connectors = {
|
||||
"H": {"pinlabels": ["VIN", "GND", "VOUT"]},
|
||||
"CA": {"pinlabels": ["X", "Y"]},
|
||||
"CB": {"pinlabels": ["M", "N"]},
|
||||
}
|
||||
connections = [
|
||||
[{"H": [1, 2]}, {"W1": [1, 2]}, {"CA": [1, 2]}],
|
||||
[{"H": [2, 3]}, {"W2": [1, 2]}, {"CB": [1, 2]}],
|
||||
]
|
||||
result_c, _, result_cn = _optimize_single_layout(
|
||||
"H", connectors, {}, connections
|
||||
)
|
||||
# Should not crash, and all pin indices must be valid
|
||||
h_labels = result_c["H"]["pinlabels"]
|
||||
assert len(h_labels) == 3
|
||||
# All connections should have valid pin references
|
||||
for conn in result_cn:
|
||||
h_pins = conn[0]["H"]
|
||||
pin_list = [h_pins] if isinstance(h_pins, int) else h_pins
|
||||
for p in pin_list:
|
||||
assert 1 <= p <= 3, f"Header pin {p} out of range"
|
||||
|
||||
def test_remap_pins_missing_key_raises(self):
|
||||
"""_remap_pins should raise ValueError with context on missing pin."""
|
||||
mapping = {1: 2, 2: 1}
|
||||
with pytest.raises(ValueError, match="Pin remapping failed for J1"):
|
||||
_remap_pins("J1", [1, 3], mapping)
|
||||
|
||||
def test_remap_pins_scalar(self):
|
||||
"""_remap_pins should handle scalar pin input."""
|
||||
mapping = {1: 3, 2: 1, 3: 2}
|
||||
assert _remap_pins("X", 2, mapping) == 1
|
||||
|
||||
def test_comp_pin_fanout_averaging(self):
|
||||
"""Component pin connecting to multiple header pins should use average."""
|
||||
# CX pin 1 connects to header pins 4 and 5 → remapped avg = 2.5
|
||||
# CX pin 2 connects to header pin 1 → remapped pos = 1.0
|
||||
# After header regrouping [1,4,5] → positions [1,2,3]:
|
||||
# pin 1: avg(2,3) = 2.5, pin 2: pos(1) = 1.0
|
||||
# So pin 2 should come before pin 1 → [P2, P1]
|
||||
connectors = {
|
||||
"H": {"pinlabels": ["A", "B", "C", "D", "E"]},
|
||||
"CX": {"pinlabels": ["P1", "P2"]},
|
||||
}
|
||||
connections = [
|
||||
[{"H": 4}, {"W1": 1}, {"CX": 1}],
|
||||
[{"H": 5}, {"W2": 1}, {"CX": 1}],
|
||||
[{"H": 1}, {"W3": 1}, {"CX": 2}],
|
||||
]
|
||||
result_c, _, _ = _optimize_single_layout("H", connectors, {}, connections)
|
||||
# Pin 2 (remapped h_pos=1.0) before Pin 1 (avg remapped h_pos=2.5)
|
||||
assert result_c["CX"]["pinlabels"] == ["P2", "P1"]
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user