Ryan Malloy
b9154e851b
C1: Port count mismatch now emits ERROR to stderr and marks
unconnected ports as __UNCONNECTED_<name>__ (never silent)
C2: Single-module pin mapping built in lockstep — cable_wires
always matches header_pins length, warns on unmappable nets
C3: VSS removed from is_power_net (it's ground per CMOS convention),
dead _POWER_PATTERN regex replaced with _KNOWN_NET_PATTERN
C4: apply_filters dead computation removed, docstring clarifies
that net-level filtering is a mapper concern
I3: WireViz render catches (ValueError, TypeError, OSError) with
diagnostic context instead of bare Exception
I5: Invalid --format flags now warn and error instead of silently
falling through to defaults
I6: Model/value heuristic warns on stderr when it triggers, since
signal names like ALERT or DATA could be misidentified
New tests: VSS classification, port count mismatch (C1), model/value
heuristic warning (I6), duplicate refs (S3), empty subcircuit (S2),
full pipeline determinism across 3 runs (S1)
115 tests pass, ruff clean
233 lines
8.3 KiB
Python
233 lines
8.3 KiB
Python
"""Tests for the SPICE netlist parser."""
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from pathlib import Path
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import pytest
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from spice2wireviz.parser.netlist import parse_netlist
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FIXTURES = Path(__file__).parent / "fixtures"
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class TestBasicParsing:
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def test_parse_simple_board(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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assert "amplifier_board" in netlist.subcircuit_defs
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subckt = netlist.subcircuit_defs["amplifier_board"]
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assert subckt.port_names == ["VIN", "GND", "VOUT", "SIGNAL_IN"]
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def test_parse_boundary_components(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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subckt = netlist.subcircuit_defs["amplifier_board"]
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refs = [c.reference for c in subckt.boundary_components]
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assert "J1" in refs
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assert "J2" in refs
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assert "TP1" in refs
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assert len(subckt.boundary_components) == 3
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def test_boundary_component_nodes(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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subckt = netlist.subcircuit_defs["amplifier_board"]
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j1 = next(c for c in subckt.boundary_components if c.reference == "J1")
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assert j1.nodes == ["VIN", "GND"]
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assert j1.value == "PWR_CONN"
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def test_test_point_single_node(self):
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netlist = parse_netlist(FIXTURES / "simple_board.net")
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subckt = netlist.subcircuit_defs["amplifier_board"]
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tp1 = next(c for c in subckt.boundary_components if c.reference == "TP1")
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assert tp1.nodes == ["N001"]
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assert tp1.prefix == "TP"
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class TestMultiBoardParsing:
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def test_parse_multi_board(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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assert len(netlist.subcircuit_defs) == 3
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assert "power_supply" in netlist.subcircuit_defs
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assert "amplifier" in netlist.subcircuit_defs
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assert "io_board" in netlist.subcircuit_defs
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def test_instances(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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refs = [inst.reference for inst in netlist.instances]
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assert "X1" in refs
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assert "X2" in refs
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assert "X3" in refs
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def test_instance_port_mapping(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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x2 = next(i for i in netlist.instances if i.reference == "X2")
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assert x2.subcircuit_name == "amplifier"
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assert x2.port_to_net == {"VIN": "VCC", "GND": "GND", "VOUT": "AUDIO_OUT"}
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def test_top_level_components(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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refs = [c.reference for c in netlist.top_level_components]
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assert "J_CHASSIS" in refs
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assert "TP_VCC" in refs
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def test_top_level_connector_nodes(self):
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netlist = parse_netlist(FIXTURES / "multi_board.net")
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j_chassis = next(c for c in netlist.top_level_components if c.reference == "J_CHASSIS")
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assert "GND" in j_chassis.nodes
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assert "EARTH" in j_chassis.nodes
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class TestHierarchicalParsing:
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def test_global_nets(self):
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netlist = parse_netlist(FIXTURES / "hierarchical.net")
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assert "VCC" in netlist.global_nets
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assert "GND" in netlist.global_nets
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def test_continuation_lines(self):
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netlist = parse_netlist(FIXTURES / "hierarchical.net")
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reg = netlist.subcircuit_defs["regulator"]
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# The continuation line should have been joined
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assert "ENABLE" in reg.parameters or len(reg.port_names) >= 3
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def test_inline_comments(self):
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"""Inline ; comments should be stripped."""
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netlist = parse_netlist(FIXTURES / "hierarchical.net")
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assert "main_board" in netlist.subcircuit_defs
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def test_all_subcircuits_found(self):
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netlist = parse_netlist(FIXTURES / "hierarchical.net")
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assert len(netlist.subcircuit_defs) == 3
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assert "regulator" in netlist.subcircuit_defs
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assert "sensor_module" in netlist.subcircuit_defs
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assert "main_board" in netlist.subcircuit_defs
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class TestStringParsing:
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def test_parse_from_string(self):
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text = """\
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.subckt simple A B
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J1 A B CONN
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.ends simple
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"""
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netlist = parse_netlist(text)
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assert "simple" in netlist.subcircuit_defs
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subckt = netlist.subcircuit_defs["simple"]
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assert subckt.port_names == ["A", "B"]
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assert len(subckt.boundary_components) == 1
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def test_empty_netlist(self):
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netlist = parse_netlist("* Just a comment\n")
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assert len(netlist.subcircuit_defs) == 0
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assert len(netlist.instances) == 0
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def test_continuation_line_joining(self):
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text = """\
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.subckt wide A B C
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+ D E F
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J1 A B CONN
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.ends wide
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"""
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netlist = parse_netlist(text)
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subckt = netlist.subcircuit_defs["wide"]
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assert subckt.port_names == ["A", "B", "C", "D", "E", "F"]
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class TestNetClassification:
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def test_ground_nets(self):
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text = ".subckt test GND AGND DGND VCC\n.ends test\n"
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netlist = parse_netlist(text)
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assert netlist.is_ground_net("GND")
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assert netlist.is_ground_net("AGND")
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assert netlist.is_ground_net("0")
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assert not netlist.is_ground_net("VCC")
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def test_power_nets(self):
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text = ".subckt test VCC VDD GND\n.ends test\n"
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netlist = parse_netlist(text)
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assert netlist.is_power_net("VCC")
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assert netlist.is_power_net("VDD")
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assert not netlist.is_power_net("GND")
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assert not netlist.is_power_net("SIGNAL")
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def test_vss_is_ground_not_power(self):
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"""VSS should be classified as ground (CMOS convention), not power."""
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text = ".subckt test VSS VDD\n.ends test\n"
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netlist = parse_netlist(text)
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assert netlist.is_ground_net("VSS")
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assert not netlist.is_power_net("VSS")
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class TestEdgeCases:
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def test_nonexistent_file(self):
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with pytest.raises(FileNotFoundError):
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parse_netlist(Path("/nonexistent/file.net"))
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def test_missing_subcircuit_warning(self, capsys):
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text = """\
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X1 A B C undefined_subckt
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"""
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netlist = parse_netlist(text)
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assert len(netlist.instances) == 1
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captured = capsys.readouterr()
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assert "undefined_subckt" in captured.err
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def test_x_instance_without_subckt_def(self):
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text = "X1 NET1 NET2 NET3 mystery_chip\n"
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netlist = parse_netlist(text)
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inst = netlist.instances[0]
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assert inst.subcircuit_name == "mystery_chip"
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# Without definition, uses positional port names
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assert "port1" in inst.port_to_net
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assert inst.port_to_net["port1"] == "NET1"
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def test_port_count_mismatch_fewer_nodes(self, capsys):
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"""C1: When instance has fewer nodes than subcircuit ports, warn and mark unconnected."""
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text = """\
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.subckt amp VIN GND VOUT ENABLE
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.ends amp
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X1 NET1 NET2 amp
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"""
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netlist = parse_netlist(text)
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inst = netlist.instances[0]
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captured = capsys.readouterr()
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assert "ERROR: port count mismatch" in captured.err
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assert "4 ports" in captured.err
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assert "2 nodes" in captured.err
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# Unconnected ports should be marked
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assert inst.port_to_net["VIN"] == "NET1"
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assert inst.port_to_net["GND"] == "NET2"
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assert "__UNCONNECTED_VOUT__" in inst.port_to_net["VOUT"]
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assert "__UNCONNECTED_ENABLE__" in inst.port_to_net["ENABLE"]
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def test_port_count_mismatch_more_nodes(self, capsys):
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"""C1: When instance has more nodes than subcircuit ports, warn about extras."""
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text = """\
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.subckt small A B
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.ends small
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X1 NET1 NET2 NET3 NET4 small
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"""
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parse_netlist(text)
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captured = capsys.readouterr()
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assert "ERROR: port count mismatch" in captured.err
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assert "extra nodes" in captured.err
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def test_model_value_heuristic_warning(self, capsys):
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"""I6: The model/value heuristic should warn when it triggers."""
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text = """\
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.subckt test A B
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J1 A B SOME_MODEL
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.ends test
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"""
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parse_netlist(text)
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captured = capsys.readouterr()
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assert "SOME_MODEL" in captured.err
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assert "model/value" in captured.err
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def test_duplicate_refs_both_parsed(self):
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"""S3: Duplicate reference designators should both be parsed."""
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text = """\
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J1 NET_A NET_B CONN_TYPE
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J1 NET_C NET_D CONN_TYPE
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"""
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netlist = parse_netlist(text)
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# Both should appear (parser doesn't deduplicate)
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j1_refs = [c for c in netlist.top_level_components if c.reference == "J1"]
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assert len(j1_refs) == 2
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