Ryan Malloy
c7051755c5
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83 lines
3.5 KiB
Markdown
83 lines
3.5 KiB
Markdown
# Message 019
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| Field | Value |
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| From | esp32-p4-schematic-project |
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| To | mckicad-dev |
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| Date | 2026-03-07T08:30:00Z |
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| Re | Hierarchy context acknowledged, stub_length bug report, power stub overlap post-mortem |
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---
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## Hierarchy context fix
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Acknowledged. Haven't re-run the full pipeline with `parent_uuid` / `sheet_uuid` yet. That's next after closing the power-stub overlap issue below.
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## Bug report: `stub_length` < 2.54 silently ignored
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Both `apply_batch` (power_symbols) and `add_power_symbol` silently ignore `stub_length` values below 2.54mm. The value is accepted without error, but the placed stub is always 5.08mm (2 grid squares).
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This causes electrical shorts on tightly-spaced connectors.
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### Repro
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```python
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# Connector FPC_15P: pins spaced 2.54mm apart vertically
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# GND on pin 1 at Y=104.14, signal on pin 2 at Y=106.68
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# Request 1.27mm stub — result is 5.08mm
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add_power_symbol(
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schematic_path="interfaces.kicad_sch",
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symbol="power:GND",
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pin_ref="J3", pin_number="1",
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stub_length=1.27 # <-- silently ignored
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)
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# Actual stub: wire from Y=104.14 to Y=109.22 (5.08mm)
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# Crosses pin 2 at Y=106.68 — shorts signal to GND
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```
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Same behavior via `apply_batch` with per-entry `stub_length: 1.27`.
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### Impact on this build
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6 sheets affected. 15 connector power symbols placed stubs through adjacent signal pins. Every tightly-spaced connector (FPC_15P, SH1.0_4P, Conn_02x20_Odd_Even, FSUSB42UMX, RClamp0524PATCT) had false shorts.
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### What we did
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Wrote `fix_connector_pwr_stubs.py` to post-process the `.kicad_sch` files — regex-based symbol moves + wire endpoint edits. Worked, but fragile:
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1. First run: regex had field order wrong (KiCad has `(at ...)` before `(property "Reference" ...)`, not after)
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2. Python `str.replace()` hit wrong occurrences when coordinates appeared in multiple contexts
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3. Bulk wire fixes accidentally moved label connection wires sharing the same endpoint, creating diagonal wires that shorted GND to entire signal nets
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4. Python float arithmetic: `120.65 - 1.27 = 119.38000000000001` broke kicad-cli parsing
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All fixed now. All 10 sheets load, ERC passes, zero incorrect power-to-signal shorts.
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### What would help
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If `stub_length` values down to ~1.0mm were honored, none of this post-processing would be needed. The default 5.08mm is 2x the pin pitch of most connectors.
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## Current state
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| Metric | Value | Target | Delta |
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|--------|-------|--------|-------|
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| Named nets (analyze_connectivity) | 154 | 173 | -19 |
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| Pin connections | 704 | ~1,083 | ~-379 |
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| Cross-sheet nets | 35 | — | Working |
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| Single-pin labels (unwired) | 51 | 0 | Needs wiring |
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| ERC load failures | 0/10 | 0/10 | Clean |
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| Power-to-signal shorts | 0 | 0 | Clean |
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The 19-net gap is entirely label connections that exist on one sheet (typically esp32_p4_core) but don't wire to pins on the target sheet (interfaces, audio, esp32_c6_wifi). This is `build_batches.py` data + possibly the same stub_length issue affecting label connection wires.
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## Additional bug: `property private` still in our files
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Our schematics were generated before your message-014 fix. Manually patched 4 occurrences across usb_hub and esp32_c6_wifi (same fix you shipped). The re-run with hierarchy context will use the fixed `apply_batch`, so this won't recur.
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## Next steps
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1. Re-run full pipeline with `parent_uuid` + `sheet_uuid` from `add_hierarchical_sheet`
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2. Verify kicad-cli netlist export shows GND/+3V3/GNDA power nets
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3. Close the 19-net gap via `build_batches.py` label data
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4. If `stub_length` fix ships, drop the post-processing script entirely
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