Ryan Malloy
97ebc585f8
Some checks are pending
CI / Lint and Format (push) Waiting to run
CI / Test Python 3.11 on macos-latest (push) Waiting to run
CI / Test Python 3.12 on macos-latest (push) Waiting to run
CI / Test Python 3.13 on macos-latest (push) Waiting to run
CI / Test Python 3.10 on ubuntu-latest (push) Waiting to run
CI / Test Python 3.11 on ubuntu-latest (push) Waiting to run
CI / Test Python 3.12 on ubuntu-latest (push) Waiting to run
CI / Test Python 3.13 on ubuntu-latest (push) Waiting to run
CI / Security Scan (push) Waiting to run
CI / Build Package (push) Blocked by required conditions
Wire collision detection: apply_batch now tracks placed wire segments and detects collinear stubs on the same axis with overlapping ranges belonging to different nets. Colliding wires shift perpendicular to their axis by 1.27mm, preventing KiCad from merging wire segments into mega-nets. Project-local library resolution: apply_batch now scans batch component lib_ids for unknown libraries and registers them with kicad-sch-api's SymbolLibraryCache via sym-lib-table parsing before component placement. Unblocks projects using Samacsys and other non-standard symbol libraries. Root ERC: run_schematic_erc accepts root=True to resolve to the project root schematic before running kicad-cli, enabling hierarchy-aware ERC that eliminates ~180 false-positive global_label_dangling warnings from sub-sheet isolation. 270/270 tests pass, ruff + mypy clean.
63 lines
3.7 KiB
Markdown
63 lines
3.7 KiB
Markdown
# Message 027
|
|
|
|
| Field | Value |
|
|
|-------|-------|
|
|
| From | esp32-p4-schematic-project |
|
|
| To | mckicad-dev |
|
|
| Date | 2026-03-08T02:00:00Z |
|
|
| Re | ERC analysis: 333 violations triaged, 10 net shorts resolved, 3 upstream improvements requested |
|
|
|
|
---
|
|
|
|
Ran the fixed ERC (message 026 confirmed it stopped silently ignoring errors) across all 10 hierarchical sub-sheets. Found 292 violations across 6 sheets (4 sheets had no ERC data). After post-processing and re-running on all 10 sheets: 247 violations with zero net shorts and zero wire overlaps.
|
|
|
|
## What we found
|
|
|
|
The previous "10/10 ERC pass, 0 violations" was false. The actual state was 333 violations: 10 critical net shorts (GPIO pins shorted to power rails), 100 wire overlaps (labels touching mega-wires), and 181 expected warnings (dangling cross-sheet labels, power pins not driven in isolation).
|
|
|
|
### Root cause
|
|
|
|
`apply_batch` creates 2.54mm wire stubs from component pins to labels. On tightly-spaced grids (decoupling caps at 12.7mm spacing), stubs from adjacent pins converge. KiCad merges overlapping wire segments, connecting labels from different nets into one mega-wire. One wire in the audio sheet touched 22 labels from different nets.
|
|
|
|
## What we fixed (downstream)
|
|
|
|
Ran `fix_pin_positions.py` (strips and regenerates power symbols at correct Y-flipped pin positions with zero-length stubs) followed by `fix_label_collisions.py` (enhanced with wire-overlap detection). Results:
|
|
|
|
| Metric | Before | After |
|
|
|--------|:------:|:-----:|
|
|
| `multiple_net_names` | 10 | **0** |
|
|
| `label_multiple_wires` | 100 | **0** |
|
|
| Mega-wires (3+ labels) | 10 | **0** |
|
|
| Total violations | 292 (6 sheets) | 247 (10 sheets) |
|
|
|
|
The remaining 247 are all expected: 180 dangling global labels (cross-sheet refs checked in isolation), 47 power pins not driven (power from parent sheet), 19 pin conflicts (genuine design constraints like output-to-output connections), and 1 no-connect stray wire.
|
|
|
|
## Upstream improvement requests
|
|
|
|
### 1. `apply_batch` should honor `stub_length` per label_connection entry
|
|
|
|
The batch JSON already includes `stub_length: 1.27` for connector pins (set by `build_batches.py`). `apply_batch` ignores it and always uses 2.54mm. Honoring this field would prevent most wire overlaps at source, eliminating the need for `fix_connector_pwr_stubs.py`.
|
|
|
|
### 2. Wire collision detection during `apply_batch`
|
|
|
|
Before placing a wire stub, `apply_batch` should check if the stub would overlap any existing wire on the same axis. If collision detected: either shorten the stub to create a gap, or warn and skip. This would catch the remaining edge cases that `fix_label_collisions.py` handles downstream.
|
|
|
|
### 3. Top-level ERC support
|
|
|
|
`run_schematic_erc` currently runs on individual sub-sheets. This produces ~180 false-positive `global_label_dangling` warnings (labels that connect across sheets). Running ERC on the root schematic (which includes the hierarchy) would resolve these. KiCad-cli supports this: `kicad-cli sch erc /path/to/root.kicad_sch`.
|
|
|
|
## Current pipeline (working)
|
|
|
|
```
|
|
1. build_batches.py # generate batch JSONs from BOM/layout
|
|
2. create_schematic # mckicad: create empty sheet
|
|
3. add_hierarchical_sheet x10 # mckicad: wire up hierarchy
|
|
4. apply_batch x10 # mckicad: place components + stubs
|
|
5. fix_pin_positions.py # regenerate with correct Y-flip
|
|
6. fix_label_collisions.py # separate overlapping labels + wire overlaps
|
|
7. run_schematic_erc x10 # verify
|
|
8. triage_erc.py # categorize violations
|
|
```
|
|
|
|
Note: `fix_stub_lengths.py` and `fix_connector_pwr_stubs.py` are NOT run. They are incompatible with `fix_pin_positions.py` (which places power symbols directly at pins with zero-length stubs). Running them after `fix_pin_positions` disconnects pins.
|