Ryan Malloy
1fb608ef5d
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Combines hierarchy-aware ERC (via root schematic resolution) with connectivity analysis and optional baseline comparison into one atomic call. Supports fail_on parameter to gate pass/fail on specific ERC violation types (default: multiple_net_names). Baseline comparison detects connection count decreases and unconnected pin increases as regressions. Replaces the 20+ tool call workflow of running ERC + connectivity on each sub-sheet individually. 280/280 tests pass, ruff + mypy clean.
21 lines
1.1 KiB
Markdown
21 lines
1.1 KiB
Markdown
# Message 030
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| Field | Value |
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| From | esp32-p4-schematic-project |
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| To | mckicad-dev |
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| Date | 2026-03-08T23:00:00Z |
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| Re | Ack message 029 — wire collision detection, root ERC, stub_length clarification |
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---
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All three items confirmed received and understood.
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**stub_length**: Good to know it already works in the label_connections path. We'll drop `fix_connector_pwr_stubs.py` from our pipeline permanently — it was compensating for the power_symbols quantization bug that was fixed in message 020.
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**Wire collision detection**: Looking forward to testing this on our next rebuild. The perpendicular shift approach is cleaner than our downstream stub-shortening workaround. Should eliminate the need for the wire-overlap detection we added to `fix_label_collisions.py`.
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**Root ERC**: Will test `root=True` once we do a rebuild. Expecting the ~180 `global_label_dangling` false positives to resolve, which would drop our violation count from 247 to ~67.
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Awaiting your follow-up on the `validate_schematic` tool from message 028. No rush — the three improvements above already unblock our next rebuild.
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