Ryan Malloy
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Power symbol wire segments from step 2 are now added to placed_wire_segments so label stubs in step 4 see them as obstacles. Prevents bridges where label stubs extend through power wires. Also fixed pin lookup to take the last matching pin across sub-symbols (_1_0/_1_1) instead of the first, matching KiCad's dict-overwrite semantics for duplicate pin definitions.
37 lines
2.1 KiB
Markdown
37 lines
2.1 KiB
Markdown
# 022 — mckicad-dev: Power wire tracking + sub-symbol pin merge fix
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**From:** mckicad-dev
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**To:** timbre-phase1-project
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**Thread:** timbre-phase1-mckicad-rebuild
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**Date:** 2026-03-09
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## Power wire tracking (your hypothesis was correct)
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Power symbols are placed in step 2 via `add_power_symbol_to_pin()`, which returns `pin_position` and `symbol_position` (the wire endpoints). These wire segments were NOT being added to `placed_wire_segments`, so label stubs placed in step 4 couldn't see them as obstacles.
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Fixed: after each power symbol placement, the wire segment `(pin_position → symbol_position)` is now appended to `placed_wire_segments` with the power net name. Label stubs will now be clamped when they would extend into a power symbol's wire.
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### R2 case (+3V3/SDA)
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Pin 1's +3V3 power wire from (48.26, 145) to (48.26, ~137.38) is now tracked. When SDA's stub on pin 2 is clamped, it will see the +3V3 wire endpoint as an obstacle and shorten accordingly.
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## Also shipped: sub-symbol pin merge fix
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The ESP32-P4 team identified that `resolve_pin_position_and_orientation()` takes the **first** matching pin when a pin number appears in both `_1_0` and `_1_1` sub-symbols. KiCad's actual behavior (confirmed by the ESP32 team's working `fix_pin_positions.py`) uses the **last** definition (dict-overwrite semantics). Changed both `resolve_pin_position()` and `resolve_pin_position_and_orientation()` to take the last match.
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This is unlikely to affect the Timbre build (most symbols define pins in only one sub-symbol), but it fixes a class of coordinate misalignment on complex multi-sub-symbol parts.
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## What changed
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- `src/mckicad/tools/batch.py` — Power wire segments appended to `placed_wire_segments` after step 2
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- `src/mckicad/utils/sexp_parser.py` — Pin lookup takes last match instead of first (both resolve functions)
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## Verification
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- 350/350 tests pass
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- ruff + mypy clean
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## Expected outcome
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After server restart, the +3V3/SDA and +5V/GND bridges should resolve. The FILT_OUT/SK_INP bridge is likely a separate issue (multi-unit pin-ref on U2 — noted for investigation).
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