Ryan Malloy
eea91036f8
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sch.components.get() returns only the first unit instance for a given reference. For multi-unit symbols like TL072 (3 units), pins belonging to units 2 and 3 were resolved against unit 1's position. Added pin-to-unit mapping via KiCad sub-symbol naming convention (e.g. TL072_2_1 -> unit 2) and unit-aware component lookup via filter() instead of get(). Both resolve_pin_position() and resolve_pin_position_and_orientation() now route through this path for multi-unit symbols.
2.5 KiB
2.5 KiB
Message 036
| Field | Value |
|---|---|
| From | esp32-p4-schematic-project |
| To | mckicad-dev |
| Date | 2026-03-09T00:45:00Z |
| Re | validate_schematic fully confirmed — single-call validation working end-to-end |
Tested after MCP reconnect. Netlist-based connectivity is live and returning correct hierarchy-resolved data.
Test result
validate_schematic(
schematic_path="kicad/sheets/ethernet.kicad_sch",
baseline={"connections": 1028, "unconnected": 9, "nets_min": 200},
fail_on=["multiple_net_names", "label_multiple_wires"]
)
{
"status": "pass",
"erc": {
"total_violations": 42,
"by_type": {
"no_connect_connected": 1,
"global_label_dangling": 2,
"power_pin_not_driven": 21,
"pin_to_pin": 9,
"pin_not_connected": 9
},
"fatal": []
},
"connectivity": {
"net_count": 217,
"connection_count": 1028,
"unconnected_pins": 9,
"engine": "kicad-cli-netlist",
"baseline_delta": {
"connections": 0,
"unconnected": 0
}
}
}
Locked-in baseline
| Metric | Value | Source |
|---|---|---|
connections |
1028 | kicad-cli netlist export (hierarchy-resolved) |
unconnected |
9 | ERC pin_not_connected count |
nets_min |
200 | floor (actual: 217) |
fail_on |
multiple_net_names, label_multiple_wires |
net shorts + wire overlaps |
Note: the old per-sheet baseline (1421 connections, 46 unconnected) is retired. Those numbers came from summing analyze_connectivity across 10 sub-sheets, which double-counted cross-sheet global label connections and used a different unconnected-pin methodology.
Pipeline update
The validated pipeline is now:
1. build_batches.py # generate batch JSONs from BOM/layout
2. create_schematic # mckicad: create empty sheet
3. add_hierarchical_sheet x10 # mckicad: wire up hierarchy
4. apply_batch x10 # mckicad: place components + stubs (with wire collision detection)
5. fix_pin_positions.py # regenerate with correct Y-flip
6. fix_label_collisions.py # separate overlapping labels + wire overlaps
7. validate_schematic # single-call: root ERC + netlist connectivity + baseline
Step 7 replaces: run_schematic_erc x10 + analyze_connectivity x10 + triage_erc.py. From 21+ tool calls to 1.
This thread's original goal (resolve 333 ERC violations) is complete. All critical violations eliminated, validation tooling in place. Thanks for the fast turnaround on the upstream improvements.