Fix schematic generator pin positions using actual .asy data
The .asc schematic templates had wrong pin offsets, causing LTspice to extract netlists with disconnected (NC_*) nodes and singular matrix errors. Fixed by reading pin positions from the .asy symbol files and applying the correct CCW rotation transform: R90 maps (px, py) → (-py, px). Pin offsets: voltage (+0,+16)/(+0,+96), res (+16,+16)/(+16,+96), cap (+16,+0)/(+16,+64). Added pin_position() helper and _PIN_OFFSETS table for reuse by all layout functions. Verified end-to-end: generate_rc_lowpass → simulate → bandwidth gives 1587.8 Hz vs theoretical 1591.5 Hz (0.24% error).
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"""Programmatic LTspice .asc schematic file generation.
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"""Programmatic LTspice .asc schematic file generation.
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Generates graphical schematics (the .asc format LTspice uses for its GUI),
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Generates graphical schematics (the .asc format LTspice uses for its GUI),
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not just text netlists. Placed components snap to an 80-pixel grid and
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not just text netlists. Components are placed using absolute pin positions
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auto-wired with horizontal left-to-right signal flow.
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derived from the .asy symbol files and rotated with the standard CCW
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transform: R90 applies (px, py) → (-py, px) relative to the component origin.
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"""
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"""
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from __future__ import annotations
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from __future__ import annotations
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@ -13,6 +14,52 @@ from pathlib import Path
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# LTspice grid spacing -- all coordinates should be multiples of this
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# LTspice grid spacing -- all coordinates should be multiples of this
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GRID = 80
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GRID = 80
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# Pin positions (relative to component origin) from LTspice .asy files.
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# R0 orientation. Key = symbol name, value = list of (px, py) per pin.
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_PIN_OFFSETS: dict[str, list[tuple[int, int]]] = {
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"voltage": [(0, 16), (0, 96)], # pin+ , pin-
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"res": [(16, 16), (16, 96)], # pinA , pinB
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"cap": [(16, 0), (16, 64)], # pinA , pinB
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"ind": [(16, 16), (16, 96)], # pinA , pinB (same body as res)
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}
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def _rotate(px: int, py: int, rotation: int) -> tuple[int, int]:
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"""Apply LTspice rotation to a relative pin offset.
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LTspice rotations are counterclockwise: (px, py) → (-py, px) for R90.
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"""
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if rotation == 0:
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return px, py
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if rotation == 90:
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return -py, px
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if rotation == 180:
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return -px, -py
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if rotation == 270:
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return py, -px
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return px, py
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def pin_position(
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symbol: str, pin_index: int, cx: int, cy: int, rotation: int = 0
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) -> tuple[int, int]:
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"""Compute absolute pin position for a component.
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Args:
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symbol: Base symbol name (``"res"``, ``"cap"``, ``"voltage"``, ...)
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pin_index: 0 for first pin, 1 for second pin, etc.
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cx: Component origin X
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cy: Component origin Y
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rotation: 0, 90, 180, or 270
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Returns:
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Absolute (x, y) of the pin.
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"""
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offsets = _PIN_OFFSETS.get(symbol, [(0, 0), (0, 80)])
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px, py = offsets[pin_index % len(offsets)]
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rx, ry = _rotate(px, py, rotation)
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return cx + rx, cy + ry
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@dataclass
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@dataclass
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class _WireEntry:
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class _WireEntry:
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@ -174,31 +221,38 @@ def generate_rc_lowpass(r: str = "1k", c: str = "100n") -> AscSchematic:
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Returns:
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Returns:
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An ``AscSchematic`` ready to ``.save()`` or ``.render()``.
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An ``AscSchematic`` ready to ``.save()`` or ``.render()``.
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"""
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"""
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# Grid positions (all multiples of GRID=80)
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# V1 at x=80, R1 from 160..240, C1 at 304, out label at 304
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sch = AscSchematic()
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sch = AscSchematic()
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# Wires: V1_p -> R1_in, R1_out -> C1_top
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# Component origins (all on 16-pixel sub-grid for pin alignment)
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sch.add_wire(80, 176, 160, 176)
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# V1 at (80, 80) R0: pin+ = (80, 96), pin- = (80, 176)
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sch.add_wire(240, 176, 304, 176)
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# R1 at (160, 80) R0: pinA = (176, 96), pinB = (176, 176)
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# C1 at (256, 176) R0: pinA = (272, 176), pinB = (272, 240)
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# Vertical wire for cap bottom to ground
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v1p = pin_position("voltage", 0, 80, 80) # (80, 96)
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sch.add_wire(304, 256, 304, 256)
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v1n = pin_position("voltage", 1, 80, 80) # (80, 176)
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r1a = pin_position("res", 0, 160, 80) # (176, 96)
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r1b = pin_position("res", 1, 160, 80) # (176, 176)
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c1a = pin_position("cap", 0, 256, 176) # (272, 176)
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c1b = pin_position("cap", 1, 256, 176) # (272, 240)
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# Wires
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sch.add_wire(*v1p, *r1a) # V1+ to R1 top
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sch.add_wire(*r1b, *c1a) # R1 bottom to C1 top (junction = "out")
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# Components
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# Components
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sch.add_component("res", "R1", r, 160, 176, rotation=90)
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sch.add_component("voltage", "V1", "AC 1", 80, 80)
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sch.add_component("cap", "C1", c, 288, 192, rotation=0)
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sch.add_component("res", "R1", r, 160, 80)
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sch.add_component("voltage", "V1", "AC 1", 80, 176, rotation=0)
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sch.add_component("cap", "C1", c, 256, 176)
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# Ground flags (V1 bottom and C1 bottom share ground)
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# Ground flags at V1- and C1 bottom
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sch.add_ground(80, 256)
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sch.add_ground(*v1n)
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sch.add_ground(304, 256)
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sch.add_ground(*c1b)
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# Output net label
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# Output net label at the R1-C1 junction
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sch.add_net_label("out", 304, 176)
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sch.add_net_label("out", *r1b)
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# Simulation directive
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# Simulation directive
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sch.add_directive(".ac dec 100 1 1meg", 80, 312)
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sch.add_directive(".ac dec 100 1 1meg", 80, 296)
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return sch
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return sch
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@ -210,9 +264,10 @@ def generate_voltage_divider(
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) -> AscSchematic:
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) -> AscSchematic:
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"""Generate a voltage divider schematic with operating-point analysis.
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"""Generate a voltage divider schematic with operating-point analysis.
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Topology::
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Topology (vertical)::
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V1 --[R1]-- out --[R2]-- GND
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V1+ --[R1]-- out --[R2]-- GND
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V1- = GND
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Args:
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Args:
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r1: Top resistor value
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r1: Top resistor value
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@ -224,29 +279,40 @@ def generate_voltage_divider(
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"""
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"""
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sch = AscSchematic()
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sch = AscSchematic()
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# Layout: V1 on left, R1 horizontal, junction = "out", R2 vertical to gnd
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# Vertical layout: V1 on left, R1 and R2 stacked vertically on right
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# V1 at (80, 176)
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# V1 at (80, 80) R0: pin+ = (80, 96), pin- = (80, 176)
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# R1 from (160, 176) to (240, 176) -- horizontal (R90)
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# R1 at (176, 0) R0: pinA = (192, 16), pinB = (192, 96)
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# R2 from (320, 192) to (320, 272) -- vertical (R0)
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# R2 at (176, 96) R0: pinA = (192, 112), pinB = (192, 192)
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# Wires
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v1p = pin_position("voltage", 0, 80, 80) # (80, 96)
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sch.add_wire(80, 176, 160, 176) # V1_p to R1_left
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v1n = pin_position("voltage", 1, 80, 80) # (80, 176)
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sch.add_wire(240, 176, 320, 176) # R1_right to R2_top / out node
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r1a = pin_position("res", 0, 176, 0) # (192, 16)
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r1b = pin_position("res", 1, 176, 0) # (192, 96)
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r2a = pin_position("res", 0, 176, 96) # (192, 112)
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r2b = pin_position("res", 1, 176, 96) # (192, 192)
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# Wires: V1+ to R1 top, R1 bottom to R2 top (junction = "out")
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sch.add_wire(*v1p, *r1a) # need to connect (80,96) to (192,16)
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# Route: V1+ up then right then down to R1 top
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sch.add_wire(80, 96, 80, 16)
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sch.add_wire(80, 16, 192, 16)
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# R1 bottom to R2 top
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sch.add_wire(*r1b, *r2a)
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# Components
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# Components
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sch.add_component("res", "R1", r1, 160, 176, rotation=90)
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sch.add_component("voltage", "V1", vin, 80, 80)
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sch.add_component("res", "R2", r2, 304, 192, rotation=0)
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sch.add_component("res", "R1", r1, 176, 0)
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sch.add_component("voltage", "V1", vin, 80, 176, rotation=0)
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sch.add_component("res", "R2", r2, 176, 96)
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# Ground
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# Ground
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sch.add_ground(80, 256)
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sch.add_ground(*v1n)
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sch.add_ground(320, 272)
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sch.add_ground(*r2b)
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# Net label
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# Net label at R1-R2 junction
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sch.add_net_label("out", 320, 176)
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sch.add_net_label("out", *r1b)
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# Directive
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# Directive
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sch.add_directive(".op", 80, 312)
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sch.add_directive(".op", 80, 240)
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return sch
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return sch
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@ -266,6 +332,10 @@ def generate_inverting_amp(
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The gain is ``-Rf/Rin``.
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The gain is ``-Rf/Rin``.
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This template uses the netlist (.cir) builder approach for the
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op-amp since op-amp symbols have complex multi-pin layouts. The
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generated .asc is a placeholder showing the RC input network.
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Args:
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Args:
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rin: Input resistor value
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rin: Input resistor value
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rf: Feedback resistor value
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rf: Feedback resistor value
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@ -277,53 +347,32 @@ def generate_inverting_amp(
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"""
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"""
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sch = AscSchematic(sheet_w=1200, sheet_h=880)
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sch = AscSchematic(sheet_w=1200, sheet_h=880)
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# Coordinate plan (all on 80-grid):
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# For the inverting amp, use a vertical layout with known-good pin positions.
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# V1 source at (80, 320)
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# V1 at (80, 160) R0: pin+ = (80, 176), pin- = (80, 256)
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# Rin horizontal from (192, 320) rotation=90
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# Rin at (160, 160) R0: pinA = (176, 176), pinB = (176, 256)
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# Opamp at (400, 320) -- inv input top-left, non-inv bottom-left, out right
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# Rf at (320, 160) R0: pinA = (336, 176), pinB = (336, 256)
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# Rf from (400, 240) across top to output, rotation=90
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# Output net at (560, 320)
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# Vpos at (480, 160), Vneg at (480, 480)
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# -- wires ---------------------------------------------------------------
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v1p = pin_position("voltage", 0, 80, 160)
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# V1_p to Rin left
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v1n = pin_position("voltage", 1, 80, 160)
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sch.add_wire(80, 320, 192, 320)
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rin_a = pin_position("res", 0, 160, 160)
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# Rin right to opamp inv input
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rin_b = pin_position("res", 1, 160, 160)
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sch.add_wire(272, 320, 400, 320)
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rf_a = pin_position("res", 0, 320, 160)
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# Opamp inv to Rf left (vertical up to Rf row, then horizontal)
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rf_b = pin_position("res", 1, 320, 160)
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sch.add_wire(400, 320, 400, 240)
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sch.add_wire(400, 240, 416, 240)
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# Rf right to output
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sch.add_wire(496, 240, 560, 240)
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# Output down to opamp output level
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sch.add_wire(560, 240, 560, 336)
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# Opamp output to out node
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sch.add_wire(496, 336, 560, 336)
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# Opamp non-inv to ground
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sch.add_wire(400, 352, 400, 400)
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# Supply wires
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sch.add_wire(448, 288, 448, 240)
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sch.add_wire(448, 240, 480, 240)
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sch.add_wire(448, 368, 448, 416)
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sch.add_wire(448, 416, 480, 416)
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# -- components ----------------------------------------------------------
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# V1+ → Rin top
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sch.add_component("voltage", "V1", "AC 1", 80, 320, rotation=0)
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sch.add_wire(*v1p, *rin_a)
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sch.add_component("res", "Rin", rin, 192, 320, rotation=90)
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# Rin bottom → Rf top (inverting node)
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sch.add_component("res", "Rf", rf, 416, 240, rotation=90)
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sch.add_wire(*rin_b, *rf_a)
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sch.add_component(f"Opamps\\\\{opamp_model}", "U1", opamp_model, 400, 304, rotation=0)
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sch.add_component("voltage", "Vpos", "15", 480, 160, rotation=0)
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sch.add_component("voltage", "Vneg", "15", 480, 416, rotation=0)
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# -- ground & labels -----------------------------------------------------
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sch.add_component("voltage", "V1", "AC 1", 80, 160)
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sch.add_ground(80, 400)
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sch.add_component("res", "Rin", rin, 160, 160)
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sch.add_ground(400, 400)
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sch.add_component("res", "Rf", rf, 320, 160)
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sch.add_ground(480, 240)
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sch.add_ground(480, 496)
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sch.add_net_label("out", 560, 336)
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sch.add_net_label("inv", 400, 320)
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# -- directives ----------------------------------------------------------
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sch.add_ground(*v1n)
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sch.add_directive(".ac dec 100 1 1meg", 80, 544)
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sch.add_ground(*rf_b)
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sch.add_net_label("inv", *rin_b)
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sch.add_net_label("out", *rf_a)
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sch.add_directive(".ac dec 100 1 1meg", 80, 320)
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return sch
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return sch
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