Second oscilloscope skin: 1959 Type 545A with blue-green hammertone
panel, cream silk-screened labels, Bakelite knobs, deeper CRT recess,
and ventilation holes. Click the model name to cycle between 465 and
545A skins. Selection persists via localStorage.
XY-mode Lissajous display renders stereo audio on a canvas
inside a warm champagne bezel with recessed CRT bay, labeled
control sections (Vertical/Horizontal/Trigger), rotary knobs,
and power LED. Uses modern AnalyserNode + rAF pipeline instead
of deprecated ScriptProcessor.
Audio: "Spirals" by Jerobeam Fenderson (CC BY-NC-SA 4.0)
Visual: Nick Watton, adapted from gist by rsp2k
COPY patches/ before npm ci so the postinstall Starlight
head.ts patch runs during install. Replace duplicate Tutorials
card on the landing page with a Concepts card.
Astro/Starlight documentation at docs/ with 21 pages:
- Getting started (prerequisites, Claude Code setup, first simulation)
- Tutorials (filter design, Monte Carlo yield)
- Reference (all 37 tools, 5 resources, 7 prompts)
- Concepts (LTspice on Linux, simulation types)
Docker infrastructure with dev/prod compose overlays, Caddy
reverse proxy for mcltspice.warehack.ing, and Makefile targets.
Includes patch for Starlight 0.37 head schema default bug.
Tools organized by category: simulation, waveform extraction,
signal analysis, noise, stability/power, schematic/netlist,
and library/templates. Added resources and prompts tables.
Rename package from mcp-ltspice/mcp_ltspice to mcltspice throughout:
source directory, imports, pyproject.toml, tests, and README.
Remove startup banner prints from main() since FastMCP handles
its own banner and stdout is the MCP JSON-RPC transport.
Point repo URL at git.supported.systems/MCP/mcltspice.
CE amplifier schematic: the input coupling cap CC_in was placed
horizontally (R90) at y=336 — the same y as the RB1-to-base bias
wire. Both cap pins sat on the wire, shorting the cap and allowing
Vin's 0V DC to override the bias divider, putting Q1 in cutoff.
Fix: move CC_in to vertical orientation (R0) above the base wire.
Now pinA=(400,256) and pinB=(400,320) are off the y=336 bias path.
The cap properly blocks DC while passing the 1kHz input signal.
Result: V(out) swings 2.2Vpp (gain ≈ 110) instead of stuck at Vcc.
Colpitts oscillator test: the schematic was actually working (V(out)
pp=2.05V) but the test's fallback variable selection picked V(n001)
(the Vcc rail, constant 12V) instead of V(out). Fix: look for V(out)
first since the schematic labels the collector with "out".
Integration tests: 4/4 pass, unit tests: 360/360 pass.
Add 7 new graphical schematic templates (differential amp, buck converter,
LDO regulator, H-bridge, common emitter, Colpitts oscillator) and rewrite
inverting amp to actually include an op-amp instead of just passive components.
Fix UniversalOpamp2 subcircuit error: the .asy symbol defines SpiceModel as
"level2", so SYMATTR Value must be omitted to let the built-in model name
resolve. Previously emitting SYMATTR Value UniversalOpamp2 caused LTspice
to search for a non-existent subcircuit.
Fix wire-through-pin routing bugs: vertical wires crossing intermediate
opamp/source pins auto-connect at those pins, creating unintended shorts.
Rerouted V1-to-In+ paths to avoid crossing In- pins in non-inverting,
common-emitter, Colpitts, and differential amp templates.
Refactor generate_schematic tool from hardcoded if/elif to registry dispatch
via _ASC_TEMPLATES dict, matching the _TEMPLATES pattern for netlists.
All 10 templates verified: simulate with zero errors and zero NC nodes.
255 tests pass, source lint clean.
The .asc schematic templates had wrong pin offsets, causing LTspice
to extract netlists with disconnected (NC_*) nodes and singular
matrix errors.
Fixed by reading pin positions from the .asy symbol files and applying
the correct CCW rotation transform: R90 maps (px, py) → (-py, px).
Pin offsets: voltage (+0,+16)/(+0,+96), res (+16,+16)/(+16,+96),
cap (+16,+0)/(+16,+64). Added pin_position() helper and _PIN_OFFSETS
table for reuse by all layout functions.
Verified end-to-end: generate_rc_lowpass → simulate → bandwidth gives
1587.8 Hz vs theoretical 1591.5 Hz (0.24% error).
Phase 3 features bringing the server to 27 tools:
- Stepped/multi-run .raw file parsing (.step, .mc, .temp)
- Stability analysis (gain/phase margin from AC loop gain)
- Power analysis (average, RMS, efficiency, power factor)
- Safe waveform expression evaluator (recursive-descent parser)
- Component value optimizer (binary search + coordinate descent)
- Batch simulation: parameter sweep, temperature sweep, Monte Carlo
- .asc schematic generation from templates (RC filter, divider, inverting amp)
- Touchstone .s1p/.s2p/.snp S-parameter file parsing
- 7 new netlist templates (diff amp, common emitter, buck, LDO, oscillator, H-bridge)
- Full ruff lint and format compliance across all modules
New modules:
- log_parser: Extract .meas results and errors from sim logs
- waveform_math: FFT, THD, RMS, settling time, rise time, bandwidth
- netlist: Programmatic SPICE netlist builder with templates
- models: Search 2800+ SPICE models and subcircuits in library
- diff: Compare two schematics for component/topology changes
- drc: Design rule checks (ground, floating nodes, missing values)
Server now has 18 tools, 3 resources, and 3 guided prompts.
- Handle UTF-16 LE encoded .raw file headers (Windows/Wine output)
- Fix mixed-precision transient data: float64 time + float32 signals
- Fix AC analysis: all variables stored as complex128, not mixed
- Fix schematic parser losing components at SYMBOL boundaries
- Use proper atan2 for phase calculation, report magnitude in dB
