Merge branch 'dev'

This commit is contained in:
Daniel Rojas 2020-05-30 12:07:16 +02:00
commit 4cceac05a9
39 changed files with 2531 additions and 416 deletions

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@ -31,19 +31,23 @@ wires:
W1: W1:
<<: *wire_i2c <<: *wire_i2c
type: bundle type: bundle
show_equiv: true
W2: W2:
<<: *wire_i2c <<: *wire_i2c
type: bundle type: bundle
show_equiv: true
W3: W3:
mm2: 0.14 mm2: 0.14
length: 0.2 length: 0.2
type: bundle
colors: [BK, BU, OG, VT] colors: [BK, BU, OG, VT]
type: bundle
show_equiv: true
W4: W4:
mm2: 0.5 mm2: 0.5
length: 0.35 length: 0.35
colors: [BK, RD] colors: [BK, RD]
type: bundle type: bundle
show_equiv: true
connections: connections:
- -

24
examples/ex01.gv Normal file
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@ -0,0 +1,24 @@
graph {
// Graph generated by WireViz
// https://github.com/formatc1702/WireViz
graph [bgcolor=transparent fontname=arial nodesep=0.33 rankdir=LR ranksep=2]
node [fillcolor=white fontname=arial shape=record style=filled]
edge [fontname=arial style=bold]
X1 [label="X1|{Molex KK 254|female|4-pin}|{{GND|VCC|RX|TX}|{<p1r>1|<p2r>2|<p3r>3|<p4r>4}}"]
X2 [label="X2|{Molex KK 254|female|4-pin}|{{<p1l>1|<p2l>2|<p3l>3|<p4l>4}|{GND|VCC|RX|TX}}"]
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edge [color="#000000:#666600:#000000"]
X1:p1r -- W1:w1
W1:w1 -- X2:p1l
edge [color="#000000:#ff0000:#000000"]
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W1:w2 -- X2:p2l
edge [color="#000000:#ff8000:#000000"]
X1:p3r -- W1:w3
W1:w3 -- X2:p4l
edge [color="#000000:#ffff00:#000000"]
X1:p4r -- W1:w4
W1:w4 -- X2:p3l
edge [color="#000000"]
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<!-- X1&#45;&#45;W1 -->
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<title>X1:p1r&#45;&#45;W1:ws</title>
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<title>X2</title>
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After

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27
examples/ex01.yml Normal file
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@ -0,0 +1,27 @@
nodes:
X1:
type: Molex KK 254 # more information
gender: female
pinout: [GND, VCC, RX, TX] # num_pins is implicit in pinout
X2:
type: Molex KK 254
gender: female
pinout: [GND, VCC, RX, TX]
wires:
W1:
color_code: IEC # auto-color wires based on a standard
num_wires: 4 # need to specify number of wires explicitly when using a color code
mm2: 0.25 # metric gauge, in mm^2
show_equiv: true # auto-calculate AWG equivalent from metric gauge
length: 0.2 # length in m
shield: true
connections:
-
- X1: [1-4]
- W1: [1-4]
- X2: [1,2,4,3] # crossover
- # connection from connector pin to wire shielding
- X1: 1
- W1: s

32
examples/ex02.gv Normal file
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graph {
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node [fillcolor=white fontname=arial shape=record style=filled]
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X2 [label="X2|{Molex Micro-Fit|female|2-pin}|{{<p1l>1|<p2l>2}|{GND|VCC}}"]
X3 [label="X3|{Molex Micro-Fit|female|2-pin}|{{<p1l>1|<p2l>2}|{GND|VCC}}"]
X4 [label="X4|{Molex Micro-Fit|female|2-pin}|{{<p1l>1|<p2l>2}|{GND|VCC}}"]
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edge [color="#000000:#ff0000:#000000"]
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edge [color="#000000:#ff0000:#000000"]
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edge [color="#000000:#000000:#000000"]
X1:p1r -- W3:w1
W3:w1 -- X4:p1l
edge [color="#000000:#ff0000:#000000"]
X1:p2r -- W3:w2
W3:w2 -- X4:p2l
}

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nodes:
X1: &boo
type: Molex Micro-Fit
gender: male
pinout: [GND, VCC]
X2: &con_power_f # define template
type: Molex Micro-Fit
gender: female
pinout: [GND, VCC]
X3:
<<: *con_power_f # create from template
X4:
<<: *con_power_f # create from template
wires:
W1: &wire_power # define template
colors: [BK, RD] # number of wires implicit in color list
mm2: 0.25
show_equiv: true
length: 0.2
W2:
<<: *wire_power # create from template
W3:
<<: *wire_power # create from template
connections:
-
- X1: [1-2]
- W1: [1-2]
- X2: [1-2]
-
- X1: [1-2]
- W2: [1-2]
- X3: [1-2]
-
- X1: [1-2]
- W3: [1-2]
- X4: [1-2]

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graph {
// Graph generated by WireViz
// https://github.com/formatc1702/WireViz
graph [bgcolor=transparent fontname=arial nodesep=0.33 rankdir=LR ranksep=2]
node [fillcolor=white fontname=arial shape=record style=filled]
edge [fontname=arial style=bold]
X1 [label="X1|{Molex Micro-Fit|male|2-pin}|{{GND|VCC}|{<p1r>1|<p2r>2}}"]
X2 [label="X2|{Molex Micro-Fit|female|2-pin}|{{<p1l>1|<p2l>2}|{GND|VCC}}"]
X3 [label="X3|{Molex Micro-Fit|female|2-pin}|{{<p1l>1|<p2l>2}|{GND|VCC}}"]
X4 [label="X4|{Molex Micro-Fit|female|2-pin}|{{<p1l>1|<p2l>2}|{GND|VCC}}"]
subgraph cluster_W1 {
graph [fillcolor=white label="6x | 0.25 mm² (24 AWG) | 0.2 m
" style="filled, dashed"]
node [fixedsize=true height=0 label="" shape=point width=0]
W1_w1l
W1_w1r
W1_w2l
W1_w2r
W1_w3l
W1_w3r
W1_w4l
W1_w4r
W1_w5l
W1_w5r
W1_w6l
W1_w6r
}
edge [color="#000000:#000000:#000000"]
W1_w1l -- W1_w1r [labelangle=60 labeldist=0 taillabel=" BK"]
X1:p1r -- W1_w1l:w [headlabel=" X1:1" labelangle=-60 labeldist=0]
W1_w1r:e -- X2:p1l [labelangle=60 labeldist=0 taillabel="X2:1 "]
edge [color="#000000:#ff0000:#000000"]
W1_w2l -- W1_w2r [labelangle=60 labeldist=0 taillabel=" RD"]
X1:p2r -- W1_w2l:w [headlabel=" X1:2" labelangle=-60 labeldist=0]
W1_w2r:e -- X2:p2l [labelangle=60 labeldist=0 taillabel="X2:2 "]
edge [color="#000000:#000000:#000000"]
W1_w3l -- W1_w3r [labelangle=60 labeldist=0 taillabel=" BK"]
X1:p1r -- W1_w3l:w [headlabel=" X1:1" labelangle=-60 labeldist=0]
W1_w3r:e -- X3:p1l [labelangle=60 labeldist=0 taillabel="X3:1 "]
edge [color="#000000:#ff0000:#000000"]
W1_w4l -- W1_w4r [labelangle=60 labeldist=0 taillabel=" RD"]
X1:p2r -- W1_w4l:w [headlabel=" X1:2" labelangle=-60 labeldist=0]
W1_w4r:e -- X3:p2l [labelangle=60 labeldist=0 taillabel="X3:2 "]
edge [color="#000000:#000000:#000000"]
W1_w5l -- W1_w5r [labelangle=60 labeldist=0 taillabel=" BK"]
X1:p1r -- W1_w5l:w [headlabel=" X1:1" labelangle=-60 labeldist=0]
W1_w5r:e -- X4:p1l [labelangle=60 labeldist=0 taillabel="X4:1 "]
edge [color="#000000:#ff0000:#000000"]
W1_w6l -- W1_w6r [labelangle=60 labeldist=0 taillabel=" RD"]
X1:p2r -- W1_w6l:w [headlabel=" X1:2" labelangle=-60 labeldist=0]
W1_w6r:e -- X4:p2l [labelangle=60 labeldist=0 taillabel="X4:2 "]
}

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36
examples/ex03.yml Normal file
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nodes:
X1: &boo
type: Molex Micro-Fit
gender: male
pinout: [GND, VCC]
X2: &con_power_f
type: Molex Micro-Fit
gender: female
pinout: [GND, VCC]
X3:
<<: *con_power_f
X4:
<<: *con_power_f
wires:
W1:
type: bundle # bundles are routed together, but more loosely than normal cables
num_wires: 6
colors: [BK, RD] # if number of items in color list is less than num_wires, loop colors
mm2: 0.25
show_equiv: true
length: 0.2
connections:
-
- X1: [1-2]
- W1: [1-2]
- X2: [1-2]
-
- X1: [1-2]
- W1: [3,4]
- X3: [1-2]
-
- X1: [1-2]
- W1: [5,6]
- X4: [1-2]

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</g>
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<g id="node18" class="node">
<title>W1_w3r</title>
<ellipse fill="white" stroke="black" cx="375" cy="-200.5" rx="0" ry="0"/>
</g>
<!-- W1_w3l&#45;&#45;W1_w3r -->
<g id="edge5" class="edge">
<title>W1_w3l&#45;&#45;W1_w3r</title>
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</g>
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</g>
<!-- W1_w4r -->
<g id="node20" class="node">
<title>W1_w4r</title>
<ellipse fill="white" stroke="black" cx="375" cy="-176.5" rx="0" ry="0"/>
</g>
<!-- W1_w4l&#45;&#45;W1_w4r -->
<g id="edge7" class="edge">
<title>W1_w4l&#45;&#45;W1_w4r</title>
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</g>
<!-- W1_w4r&#45;&#45;F9 -->
<g id="edge15" class="edge">
<title>W1_w4r:e&#45;&#45;F9:p1l</title>
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</g>
<!-- W1_w5r -->
<g id="node22" class="node">
<title>W1_w5r</title>
<ellipse fill="white" stroke="black" cx="375" cy="-152.5" rx="0" ry="0"/>
</g>
<!-- W1_w5l&#45;&#45;W1_w5r -->
<g id="edge9" class="edge">
<title>W1_w5l&#45;&#45;W1_w5r</title>
<path fill="none" stroke="#000000" stroke-width="2" d="M232.1,-150.5C236.34,-150.5 369.73,-150.5 373.9,-150.5"/>
<path fill="none" stroke="#00ff00" stroke-width="2" d="M232.1,-152.5C236.34,-152.5 369.73,-152.5 373.9,-152.5"/>
<path fill="none" stroke="#000000" stroke-width="2" d="M232.1,-154.5C236.34,-154.5 369.73,-154.5 373.9,-154.5"/>
<text text-anchor="middle" x="237.1" y="-157.46" font-family="arial" font-size="14.00"> &#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;GN</text>
</g>
<!-- W1_w5r&#45;&#45;F8 -->
<g id="edge14" class="edge">
<title>W1_w5r:e&#45;&#45;F8:p1l</title>
<path fill="none" stroke="#000000" stroke-width="2" d="M376,-150.5C458.19,-152.28 465.83,-82.28 552,-80.5"/>
<path fill="none" stroke="#00ff00" stroke-width="2" d="M376,-152.5C460.18,-152.5 467.82,-82.5 552,-82.5"/>
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<text text-anchor="middle" x="381.71" y="-157.01" font-family="arial" font-size="14.00">F8:1 &#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;</text>
</g>
<!-- W1_w6r -->
<g id="node24" class="node">
<title>W1_w6r</title>
<ellipse fill="white" stroke="black" cx="375" cy="-128.5" rx="0" ry="0"/>
</g>
<!-- W1_w6l&#45;&#45;W1_w6r -->
<g id="edge11" class="edge">
<title>W1_w6l&#45;&#45;W1_w6r</title>
<path fill="none" stroke="#000000" stroke-width="2" d="M232.1,-126.5C236.34,-126.5 369.73,-126.5 373.9,-126.5"/>
<path fill="none" stroke="#0066ff" stroke-width="2" d="M232.1,-128.5C236.34,-128.5 369.73,-128.5 373.9,-128.5"/>
<path fill="none" stroke="#000000" stroke-width="2" d="M232.1,-130.5C236.34,-130.5 369.73,-130.5 373.9,-130.5"/>
<text text-anchor="middle" x="237.1" y="-133.46" font-family="arial" font-size="14.00"> &#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;&#160;BU</text>
</g>
<!-- W1_w6r&#45;&#45;F7 -->
<g id="edge13" class="edge">
<title>W1_w6r:e&#45;&#45;F7:p1l</title>
<path fill="none" stroke="#000000" stroke-width="2" d="M376,-126.5C467.94,-128.7 456.08,-11.7 552,-9.5"/>
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</g>
</g>
</svg>

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32
examples/ex04.yml Normal file
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@ -0,0 +1,32 @@
# nodes:
# X1:
# type: D-Sub
# gender: female
# num_pins: 4
# X2:
# type: Molex KK 254
# gender: female
# num_pins: 3
wires:
W1:
mm2: 0.25
show_equiv: true
length: 0.2
color_code: IEC
num_wires: 6
type: bundle
ferrules:
ferrule_crimp:
type: crimp
show_name: false
show_num_pins: false
connections:
-
- ferrule_crimp
- W1: [1-6]
-
- W1: [6-1]
- ferrule_crimp

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@ -1,15 +0,0 @@
import wireviz
h = wireviz.Harness()
h.add_cable('W1', mm2=0.25, length=0.2, show_name=True, show_pinout=True, num_wires=3, color_code='DIN', shield=True)
h.add_node('X1', type='D-Sub', gender='female', pinout=('DCD','RX','TX','DTR','GND','DSR','RTS','CTS','RI'))
h.add_node('X2', type='Molex KK 254', gender='female', pinout=('GND','RX','TX','NC','OUT','IN'))
# Option 1: define wires and shield in one line
h.connect('X1',(5,2,3,5),'W1',(1,2,3,'s'),'X2',(1,3,2,None))
h.loop('X2', 5, 6)
# Option 2: define wires and shield separately
# Harness.objects['W1'].connect('X1',(5,2,3),'auto','X2',(1,3,2)) # wires
# Harness.objects['W1'].connect('X1',(5,),('s',),'X2',(None,)) # shield
h.output(filename='output', format=('png','svg'), view=False)

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@ -1,31 +0,0 @@
import wireviz
h = wireviz.Harness()
# shortcuts for use during harness creation
PINOUT_I2C = ('GND','+5V','SCL','SDA')
COLORS_I2C = ('BK', 'RD', 'YE', 'GN')
PINOUT_SPI_DATAONLY = ('MISO','MOSI','SCK')
h.add_node('X1', type='Molex KK 254', gender='female', pinout=('GND',
'+5V',
'SCL',
'SDA',
'MISO',
'MOSI',
'SCK',
'N/C'))
h.add_node('X2', type='Molex KK 254', gender='female', pinout=PINOUT_I2C)
h.add_node('X3', type='Molex KK 254', gender='female', pinout=PINOUT_I2C)
h.add_node('X4', type='Molex KK 254', gender='female', pinout=('GND','+12V')+PINOUT_SPI_DATAONLY)
h.add_node('X5', type='Molex Micro-Fit', gender='male', pinout=('GND','+12V'))
h.add_cable('W1', mm2=0.14, show_equiv=True, length=0.2, colors=COLORS_I2C, show_name=False)
h.add_cable('W2', mm2=0.14, show_equiv=True, length=0.2, colors=COLORS_I2C, show_name=False)
h.add_cable('W3', mm2=0.14, show_equiv=True, length=0.2, colors=('BK','BU','OG','VT'), show_name=False)
h.add_cable('W4', mm2=0.5, show_equiv=True, length=0.35, colors=('BK','RD'), show_name=False)
h.connect('X1',(1,2,3,4),'W1','auto','X2','auto')
h.connect('X1',(1,2,3,4),'W2','auto','X3','auto')
h.connect('X1',(1,5,6,7),'W3','auto','X4',(1,3,4,5))
h.connect_all_straight('W4','X5','X4')
h.output(filename='output', format=('png','svg'), view=False)

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@ -1,64 +0,0 @@
templates: # defining templates to be used later on
- &molex_f
type: Molex KK 254
gender: female
- &con_i2c
pinout: [GND, +5V, SCL, SDA]
- &wire_i2c
mm2: 0.14
length: 0.2
colors: [BK, RD, YE, GN]
nodes:
X1:
<<: *molex_f # copying items from the template
pinout: [GND, +5V, SCL, SDA, MISO, MOSI, SCK, N/C]
X2:
<<: *molex_f
<<: *con_i2c # it is possible to copy from more than one template
X3:
<<: *molex_f
<<: *con_i2c
X4:
<<: *molex_f
pinout: [GND, +12V, MISO, MOSI, SCK]
X5:
type: Molex Micro-Fit
gender: male
pinout: [GND, +12V]
wires:
W1:
<<: *wire_i2c
show_name: false
W2:
<<: *wire_i2c
show_name: false
W3:
mm2: 0.14
length: 0.2
colors: [BK, BU, OG, VT]
show_name: false
W4:
mm2: 0.5
length: 0.35
colors: [BK, RD]
show_name: false
connections:
-
- X1: [1-4]
- W1: [1-4]
- X2: [1-4]
-
- X1: [1-4]
- W2: [1-4]
- X3: [1-4]
-
- X1: [1,5-7]
- W3: [1-4]
- X4: [1,3-5]
-
- X5: [1,2]
- W4: [1,2]
- X4: [1,2]

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@ -1,26 +0,0 @@
import wireviz
h = wireviz.Harness()
h.color_mode = 'full'
h.add_node('X1', num_pins=10)
h.add_node('X2', num_pins=10)
h.add_cable('W1', num_wires=10, color_code='IEC')
h.connect_all_straight('W1','X1','X2')
h.add_node('X3', num_pins=20)
h.add_node('X4', num_pins=20)
h.add_cable('W2', num_wires=20, color_code='DIN')
h.connect_all_straight('W2','X3','X4')
h.add_node('X5', num_pins=20)
h.add_node('X6', num_pins=20)
h.add_cable('W3', num_wires=20, colors=('RD','YE','BU'))
h.connect_all_straight('W3','X5','X6')
h.add_node('X7', num_pins=6)
h.add_node('X8', num_pins=6)
h.add_cable('W4', num_wires=6, length=1, mm2=1)
h.connect_all_straight('W4','X7','X8')
h.output(filename='output', format=('png','svg'), view=False)

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@ -1,13 +0,0 @@
import wireviz
h = wireviz.Harness()
h.add_cable('W1', show_name=False, show_num_wires=False, num_wires=4, color_code='DIN')
h.add_cable('W2', show_name=False, show_num_wires=False, num_wires=4, color_code='DIN')
h.add_node('X1', num_pins=4, show_num_pins=False)
h.add_node('X2', num_pins=4, show_num_pins=False)
h.add_node('X3', num_pins=4, show_num_pins=False)
h.connect_all_straight('W1','X1','X2')
h.connect_all_straight('W2','X2','X3')
h.output(filename='output', format=('png','svg'), view=False)

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@ -1,34 +0,0 @@
nodes:
X1:
type: D-Sub
gender: female
num_pins: 4
X2:
type: Molex KK 254
gender: female
num_pins: 3
wires:
W1:
mm2: 0.25
show_equiv: true
length: 0.2
color_code: IEC
num_wires: 10
type: bundle
ferrules:
F_test:
type: crimp
connections:
-
- X1: [1-3]
- W1: [1-3]
- X2: [1-3]
-
- F_test
- W1: [4-10]
-
- W1: [10-4]
- F_test

25
examples/readme.md Normal file
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@ -0,0 +1,25 @@
# Example gallery
## Example 01
![](ex01.png)
[Source](ex01.yml)
## Example 02
![](ex02.png)
[Source](ex02.yml)
## Example 03
![](ex03.png)
[Source](ex03.yml)
## Example 04
![](ex04.png)
[Source](ex04.yml)

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@ -1,43 +0,0 @@
nodes:
X1:
# type: D-Sub
# gender: female
num_pins: 15
X2:
type: Molex KK 254
gender: female
num_pins: 10
wires:
W1:
mm2: 0.25
length: 0.2
color_code: DIN
num_wires: 15
shield: true
connections:
-
- X1: 1
- W1: 1
- X2: 1
-
- X1: [2,3,4]
- W1: [2,3,4]
- X2: [4,3,2]
-
- X1: [5-10]
- W1: [5-7,10,9,8]
- X2: [10-5]
-
- X1: 11
- W1: s
-
- X1: [1-5]
- W1: [11-15]
-
- W1: [12-15]
- X2: [2-5]
-
- X1: [12,14]
- X1: [13,15]

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@ -23,16 +23,17 @@ WireViz is a simple yet flexible, YAML-based markup language for documenting cab
_Note_: WireViz is not designed to represent the complete wiring of a system. Its main aim is to document the construction of individual wires and harnesses. _Note_: WireViz is not designed to represent the complete wiring of a system. Its main aim is to document the construction of individual wires and harnesses.
## Example ## Examples
[WireViz input file](examples/example1.yml): ### Demo 01
[WireViz input file](examples/demo01.yml):
nodes: nodes:
X1: X1:
type: D-Sub type: D-Sub
gender: female gender: female
pinout: [DCD, RX, TX, DTR, GND, DSR, RTS, CTS, RI] pinout: [DCD, RX, TX, DTR, GND, DSR, RTS, CTS, RI]
random: yes
X2: X2:
type: Molex KK 254 type: Molex KK 254
gender: female gender: female
@ -60,17 +61,22 @@ _Note_: WireViz is not designed to represent the complete wiring of a system. It
Output file: Output file:
![Sample output diagram](examples/example1.png) ![Sample output diagram](examples/demo01.png)
[Example 2](examples/example2.yml) ### Demo 02
![](examples/example2.png) ![](examples/demo02.png)
[Source](examples/demo02.yml)
### More examples
See the [example gallery](examples/) and included readme file.
## Status ## Status
This is very much a [work in progress](todo.md). This is very much a [work in progress](todo.md).
## License ## License
GNU GPLv3 GNU GPLv3

2
src/.gitignore vendored
View File

@ -1,2 +1,2 @@
__pycache__/ __pycache__/
_output/ _test/

21
src/batch.py Normal file
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@ -0,0 +1,21 @@
import wireviz
import os
readme = '../examples/readme.md'
readme = os.path.abspath(readme)
with open(readme, 'w') as file:
file.write('# Example gallery\n')
for i in range(1,3):
fn = '../examples/demo{:02d}.yml'.format(i)
print(fn)
wireviz.parse(fn)
for i in range(1,5):
fn = '../examples/ex{:02d}.yml'.format(i)
print(fn)
wireviz.parse(fn)
file.write('## Example {:02d}\n'.format(i))
file.write('![](ex{:02d}.png)\n\n'.format(i))
file.write('[Source](ex{:02d}.yml)\n\n\n'.format(i))

194
src/wireviz.py Normal file → Executable file
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@ -1,5 +1,8 @@
#!/usr/bin/env python3
import os
from dataclasses import dataclass, field from dataclasses import dataclass, field
from typing import Any, List from typing import Any, List
import yaml
from graphviz import Graph from graphviz import Graph
COLOR_CODES = {'DIN': ['WH','BN','GN','YE','GY','PK','BU','RD','BK','VT'], # ,'GYPK','RDBU','WHGN','BNGN','WHYE','YEBN','WHGY','GYBN','WHPK','PKBN'], COLOR_CODES = {'DIN': ['WH','BN','GN','YE','GY','PK','BU','RD','BK','VT'], # ,'GYPK','RDBU','WHGN','BNGN','WHYE','YEBN','WHGY','GYBN','WHPK','PKBN'],
@ -385,3 +388,194 @@ def awg_equiv(mm2):
return awg_equiv_table[k] return awg_equiv_table[k]
else: else:
return None return None
def parse(file_in, file_out=None):
file_in = os.path.abspath(file_in)
if not file_out:
file_out = file_in
pre, ext = os.path.splitext(file_out)
file_out = pre # extension will be added by graphviz output function
file_out = os.path.abspath(file_out)
with open(file_in, 'r') as stream:
try:
input = yaml.safe_load(stream)
except yaml.YAMLError as exc:
print(exc)
def expand(input):
# input can be:
# - a singleton (normally str or int)
# - a list of str or int
# if str is of the format '#-#', it is treated as a range (inclusive) and expanded
output = []
if not isinstance(input, list):
input = [input,]
for e in input:
e = str(e)
if '-' in e: # list of pins
a, b = tuple(map(int, e.split('-')))
if a < b:
for x in range(a,b+1):
output.append(x)
elif a > b:
for x in range(a,b-1,-1):
output.append(x)
elif a == b:
output.append(a)
else:
try:
x = int(e)
except:
x = e
output.append(x)
return output
def check_designators(what, where):
for i, x in enumerate(what):
# print('Looking for {} in {}'.format(x,where[i]))
if x not in input[where[i]]:
return False
return True
h = Harness()
# add items
sections = ['nodes','wires','ferrules','connections']
types = [dict, dict, dict, list]
for sec, ty in zip(sections, types):
if sec in input and type(input[sec]) == ty:
if len(input[sec]) > 0:
if ty == dict:
for k, o in input[sec].items():
if sec == 'nodes':
h.add_node(name=k, **o)
elif sec == 'wires':
h.add_cable(name=k, **o)
elif sec == 'ferrules':
pass
else:
print('{} section empty'.format(sec))
else:
print('No {} section found'.format(sec))
if ty == dict:
input[sec] = {}
elif ty == list:
input[sec] = []
# add connections
ferrule_counter = 0
for con in input['connections']:
if len(con) == 3: # format: connector -- wire -- conector
for c in con:
if len(list(c.keys())) != 1: # check that each entry in con has only one key, which is the designator
raise Exception('Too many keys')
from_name = list(con[0].keys())[0]
via_name = list(con[1].keys())[0]
to_name = list(con[2].keys())[0]
if not check_designators([from_name,via_name,to_name],('nodes','wires','nodes')):
raise Exception('Bad connection definition (3)')
from_pins = expand(con[0][from_name])
via_pins = expand(con[1][via_name])
to_pins = expand(con[2][to_name])
if len(from_pins) != len(via_pins) or len(via_pins) != len(to_pins):
raise Exception('List length mismatch')
for (from_pin, via_pin, to_pin) in zip(from_pins, via_pins, to_pins):
h.connect(from_name, from_pin, via_name, via_pin, to_name, to_pin)
elif len(con) == 2:
for c in con:
if type(c) is dict:
if len(list(c.keys())) != 1: # check that each entry in con has only one key, which is the designator
raise Exception('Too many keys')
# hack to make the format for ferrules compatible with the formats for connectors and wires
if type(con[0]) == str:
name = con[0]
con[0] = {}
con[0][name] = name
if type(con[1]) == str:
name = con[1]
con[1] = {}
con[1][name] = name
from_name = list(con[0].keys())[0]
to_name = list(con[1].keys())[0]
n_w = check_designators([from_name, to_name],('nodes','wires'))
w_n = check_designators([from_name, to_name],('wires','nodes'))
n_n = check_designators([from_name, to_name],('nodes','nodes'))
f_w = check_designators([from_name, to_name],('ferrules','wires'))
w_f = check_designators([from_name, to_name],('wires','ferrules'))
if not n_w and not w_n and not n_n and not f_w and not w_f:
raise Exception('Wrong designators')
from_pins = expand(con[0][from_name])
to_pins = expand(con[1][to_name])
if n_w or w_n or n_n:
if len(from_pins) != len(to_pins):
raise Exception('List length mismatch')
if n_w or w_n:
for (from_pin, to_pin) in zip(from_pins, to_pins):
if n_w:
h.connect(from_name, from_pin, to_name, to_pin, None, None)
else: # w_n
h.connect(None, None, from_name, from_pin, to_name, to_pin)
elif n_n:
con_name = list(con[0].keys())[0]
from_pins = expand(con[0][from_name])
to_pins = expand(con[1][to_name])
for (from_pin, to_pin) in zip(from_pins, to_pins):
h.loop(con_name, from_pin, to_pin)
if f_w or w_f:
from_pins = expand(con[0][from_name])
to_pins = expand(con[1][to_name])
if f_w:
ferrule_name = from_name
wire_name = to_name
wire_pins = to_pins
else:
ferrule_name = to_name
wire_name = from_name
wire_pins = from_pins
ferrule_params = input['ferrules'][ferrule_name]
for wire_pin in wire_pins:
ferrule_counter = ferrule_counter + 1
ferrule_id = 'F{}'.format(ferrule_counter)
h.add_node(ferrule_id, **ferrule_params)
if f_w:
h.connect(ferrule_id, 1, wire_name, wire_pin, None, None)
else:
h.connect(None, None, wire_name, wire_pin, ferrule_id, 1)
else:
raise Exception('Wrong number of connection parameters')
h.output(filename=file_out, format=('png','svg'), view=False)
if __name__ == '__main__':
import argparse
ap = argparse.ArgumentParser()
ap.add_argument('file_input', nargs='?', default='_test/test.yml')
ap.add_argument('file_output', nargs='?', default=None)
args = ap.parse_args()
parse(args.file_input, args.file_output)

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@ -1,180 +0,0 @@
import yaml
import wireviz
filename = '../examples/example1.yml'
filename = '../examples/example2.yml'
filename = '../examples/ferrules.yml'
filename = '../examples/bundles.yml'
def check_designators(what, where):
for i, x in enumerate(what):
# print('Looking for {} in {}'.format(x,where[i]))
if x not in input[where[i]]:
return False
return True
def expand(input):
# input can be:
# - a singleton (normally str or int)
# - a list of str or int
# if str is of the format '#-#', it is treated as a range (inclusive) and expanded
output = []
if not isinstance(input, list):
input = [input,]
for e in input:
e = str(e)
if '-' in e: # list of pins
a, b = tuple(map(int, e.split('-')))
if a < b:
for x in range(a,b+1):
output.append(x)
elif a > b:
for x in range(a,b-1,-1):
output.append(x)
elif a == b:
output.append(a)
else:
try:
x = int(e)
except:
x = e
output.append(x)
return output
with open(filename, 'r') as stream:
try:
input = yaml.safe_load(stream)
except yaml.YAMLError as exc:
print(exc)
h = wireviz.Harness()
# add items
sections = ['nodes','wires','ferrules','connections']
types = [dict, dict, dict, list]
for sec, ty in zip(sections, types):
if sec in input and type(input[sec]) == ty:
if len(input[sec]) > 0:
if ty == dict:
for k, o in input[sec].items():
if sec == 'nodes':
h.add_node(name=k, **o)
elif sec == 'wires':
h.add_cable(name=k, **o)
elif sec == 'ferrules':
pass
else:
print('{} section empty'.format(sec))
else:
print('No {} section found'.format(sec))
if ty == dict:
input[sec] = {}
elif ty == list:
input[sec] = []
# add connections
ferrule_counter = 0
for con in input['connections']:
if len(con) == 3: # format: connector -- wire -- conector
for c in con:
if len(list(c.keys())) != 1: # check that each entry in con has only one key, which is the designator
raise Exception('Too many keys')
from_name = list(con[0].keys())[0]
via_name = list(con[1].keys())[0]
to_name = list(con[2].keys())[0]
if not check_designators([from_name,via_name,to_name],('nodes','wires','nodes')):
raise Exception('Bad connection definition (3)')
from_pins = expand(con[0][from_name])
via_pins = expand(con[1][via_name])
to_pins = expand(con[2][to_name])
if len(from_pins) != len(via_pins) or len(via_pins) != len(to_pins):
raise Exception('List length mismatch')
for (from_pin, via_pin, to_pin) in zip(from_pins, via_pins, to_pins):
h.connect(from_name, from_pin, via_name, via_pin, to_name, to_pin)
elif len(con) == 2:
for c in con:
if type(c) is dict:
if len(list(c.keys())) != 1: # check that each entry in con has only one key, which is the designator
raise Exception('Too many keys')
# hack to make the format for ferrules compatible with the formats for connectors and wires
if type(con[0]) == str:
name = con[0]
con[0] = {}
con[0][name] = name
if type(con[1]) == str:
name = con[1]
con[1] = {}
con[1][name] = name
from_name = list(con[0].keys())[0]
to_name = list(con[1].keys())[0]
n_w = check_designators([from_name, to_name],('nodes','wires'))
w_n = check_designators([from_name, to_name],('wires','nodes'))
n_n = check_designators([from_name, to_name],('nodes','nodes'))
f_w = check_designators([from_name, to_name],('ferrules','wires'))
w_f = check_designators([from_name, to_name],('wires','ferrules'))
if not n_w and not w_n and not n_n and not f_w and not w_f:
raise Exception('Wrong designators')
from_pins = expand(con[0][from_name])
to_pins = expand(con[1][to_name])
if n_w or w_n or n_n:
if len(from_pins) != len(to_pins):
raise Exception('List length mismatch')
if n_w or w_n:
for (from_pin, to_pin) in zip(from_pins, to_pins):
if n_w:
h.connect(from_name, from_pin, to_name, to_pin, None, None)
else: # w_n
h.connect(None, None, from_name, from_pin, to_name, to_pin)
elif n_n:
con_name = list(con[0].keys())[0]
from_pins = expand(con[0][from_name])
to_pins = expand(con[1][to_name])
for (from_pin, to_pin) in zip(from_pins, to_pins):
h.loop(con_name, from_pin, to_pin)
if f_w or w_f:
from_pins = expand(con[0][from_name])
to_pins = expand(con[1][to_name])
if f_w:
ferrule_name = from_name
wire_name = to_name
wire_pins = to_pins
else:
ferrule_name = to_name
wire_name = from_name
wire_pins = from_pins
ferrule_params = input['ferrules'][ferrule_name]
for wire_pin in wire_pins:
ferrule_counter = ferrule_counter + 1
ferrule_id = 'F{}'.format(ferrule_counter)
h.add_node(ferrule_id, **ferrule_params)
if f_w:
h.connect(ferrule_id, 1, wire_name, wire_pin, None, None)
else:
h.connect(None, None, wire_name, wire_pin, ferrule_id, 1)
else:
raise Exception('Wrong number of connection parameters')
h.output(filename='output', format=('png','svg'), view=False)