rsp2k
f79134fee6
Rotated oval pads were built from padded corners that are not in outline order, so they fell back to their bounding box; neighbouring boxes of a rotated socket overlap, and the grid's own-pad exemption opened the overlap to the pin's net, which the exact check then refused. Pads are now the convex hull of their corners, the exact tree checks a rotated pad against that outline, and the grid blocks cells against the same outline. A via reused by a second connection of its net left that connection with no claim on the via's footprint, so ripping the first owner freed cells around a via still on the board. Footprint cells now keep every claimant. A net class wider than the default was searched as a default trace: its spread was empty below half a cell, halos were circular while the exact check compares boxes, and a rip-up route only counted what its centre crossed. The spread now covers the extra width in whole cells, halos are square, and rip-up victims include what the spread crosses. bench/diagnose.py now routes with net-class widths and hole spacing, as the CLI does.
228 lines
9.3 KiB
Python
228 lines
9.3 KiB
Python
"""The grid must not believe copper legal that the exact check then refuses.
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Each case is one way the two used to disagree on roomba-ESP12E: a rotated oval
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pad modelled as an inflated box (and opened to its own net), a via shared by
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two connections of a net losing its footprint when one of them is ripped, and
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a wider net class searched as if it were the default width.
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"""
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from __future__ import annotations
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import math
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import pytest
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from freeroute.board import build_board
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from freeroute.dsn import parse_dsn
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from freeroute.geometry import IntBox, Simplex
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from freeroute.route.grid_router import GridRouter
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from freeroute.route.pipeline import (
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_rule_clearance_dsn,
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_rule_width_dsn,
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_via_half_board,
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build_exact_routing_result,
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)
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# --- rotated oval pads -------------------------------------------------------
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def _socket_dsn(rotation: float, layout: str) -> str:
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"""A 1x4 2.54 mm socket strip (rect pin 1, oval pins 2-4) at ``rotation``,
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each pin its own net, routed to a small SMD pad 0.9 mm away."""
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cx, cy = 100000, -100000
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t = math.radians(rotation)
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ax = (math.cos(t), math.sin(t))
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perp = (-math.sin(t), math.cos(t))
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places = []
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for i in range(4):
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px, py = cx + 2540 * i * ax[0], cy + 2540 * i * ax[1]
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side = 1 if i % 2 == 0 else -1
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if layout == "y":
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tx, ty = px, py + side * 9000
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else:
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tx, ty = px + side * 8000 * perp[0], py + side * 8000 * perp[1]
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places.append(f"(place T{i + 1} {round(tx)} {round(ty)} front 0)")
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nets = " ".join(f"(net N{i} (pins P3-{i + 1} T{i + 1}-1))" for i in range(4))
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return f"""(pcb socket (parser) (resolution um 10) (unit um)
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(structure
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(layer F.Cu (type signal)) (layer B.Cu (type signal))
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(boundary (path pcb 0 125000 -115000 85000 -115000 85000 -75000 125000 -75000
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125000 -115000))
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(via "Via[0-1]_800:400_um")
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(rule (width 300) (clearance 250)))
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(placement
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(component S (place P3 {cx} {cy} front {rotation}))
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(component T {" ".join(places)}))
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(library
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(image S (pin R 1 0 0) (pin O 2 2540 0) (pin O 3 5080 0) (pin O 4 7620 0))
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(image T (pin t 1 0 0))
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(padstack O (shape (path F.Cu 1727.2 0 -152.4 0 152.4))
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(shape (path B.Cu 1727.2 0 -152.4 0 152.4)) (attach off))
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(padstack R (shape (rect F.Cu -863.6 -1016 863.6 1016))
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(shape (rect B.Cu -863.6 -1016 863.6 1016)) (attach off))
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(padstack t (shape (rect F.Cu -500 -500 500 500)) (attach off))
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(padstack "Via[0-1]_800:400_um" (shape (circle F.Cu 800)) (shape (circle B.Cu 800))
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(attach off)))
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(network {nets}
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(class c N0 N1 N2 N3 (circuit (use_via "Via[0-1]_800:400_um"))
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(rule (width 300) (clearance 250)))))"""
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def test_a_rotated_oval_pad_is_its_outline_not_its_bounding_box():
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board = build_board(parse_dsn(_socket_dsn(60, "y")))
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oval = next(p for p in board.get_pins() if p.component_ref == "P3" and p.name == "2")
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assert isinstance(oval.shape, Simplex) and not oval.shape.is_int_box()
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box = oval.shape.bounding_box()
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assert oval.shape.contains(oval.location)
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assert not oval.shape.contains(box.ll) and not oval.shape.contains(box.ur)
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@pytest.mark.parametrize("layout", ["y", "perp"])
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def test_routes_leaving_a_rotated_socket_pass_the_exact_check(layout):
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result = build_exact_routing_result(
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parse_dsn(_socket_dsn(60, layout)), resolution=2, shove=True
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)
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assert result.unrouted == []
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# --- a via two connections share --------------------------------------------
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_SHARED_VIA = """(pcb shared (parser) (resolution um 10) (unit um)
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(structure
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(layer Top (type signal)) (layer Bottom (type signal))
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(boundary (path pcb 0 0 0 20000 0 20000 -20000 0 -20000 0 0))
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(via "Via[0-1]_800:400_um")
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(rule (width 300) (clearance 250)))
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(library
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(padstack p (shape (rect Top -400 -400 400 400)) (attach off))
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(padstack "Via[0-1]_800:400_um" (shape (circle Top 800)) (shape (circle Bottom 800))
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(attach off))
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(image PAD (pin p 1 0 0)))
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(placement (component PAD
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(place G1 3000 -5000 front 0) (place G2 3000 -15000 front 0)
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(place G3 17000 -10000 front 0) (place S1 3000 -10000 front 0)
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(place S2 17000 -3000 front 0)))
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(network (net GND (pins G1-1 G2-1 G3-1)) (net SIG (pins S1-1 S2-1))))"""
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def _line(a, b, layer):
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(x, y), (x1, y1) = a, b
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out = [(x, y, layer)]
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while x != x1:
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x += 1 if x1 > x else -1
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out.append((x, y, layer))
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while y != y1:
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y += 1 if y1 > y else -1
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out.append((x, y, layer))
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return out
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def test_a_shared_via_keeps_its_footprint_when_one_user_is_ripped():
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dsn = parse_dsn(_SHARED_VIA)
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s = dsn.resolution.value
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router = GridRouter(
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build_board(dsn),
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trace_width=round(_rule_width_dsn(dsn) * s),
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clearance=round(_rule_clearance_dsn(dsn) * s),
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via_half=_via_half_board(dsn, s),
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)
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conns = router._conns = router._build_connections()
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gnd = [c for c in conns if len({c.a.component_ref, c.b.component_ref} & {"G1", "G2", "G3"})]
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sig = next(c for c in conns if c not in gnd)
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first, second = gnd
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g3 = router._cell_of(next(p for p in router.board.get_pins() if p.component_ref == "G3").location)
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via = (g3[0] - 10, g3[1])
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def through_via(conn):
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a, b = router._cell_of(conn.a.location), router._cell_of(conn.b.location)
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return _line(a, via, 0) + _line(via, b, 1)
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router._commit(first, through_via(first))
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router._commit(second, through_via(second))
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footprint = [c for c in router._via_cells(via) if c != via]
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router._rip(first)
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assert second.routed and via in second.via_cells
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assert all(router._via_owner.get(c) == second.index for c in footprint)
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# another net still keeps its distance from the via that is left
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assert all(router._enter_cost_base(c, 0, sig.net_no, False, conns) is None for c in footprint)
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# --- a wider net class --------------------------------------------------------
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_WIDE = """(pcb wide (parser) (resolution um 10) (unit um)
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(structure
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(layer F.Cu (type signal))
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(boundary (path pcb 0 0 0 20000 0 20000 -10000 0 -10000 0 0))
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(rule (width 300) (clearance 250)))
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(placement (component S (place P1 2000 -5000 front 0) (place P2 18000 -5000 front 0)
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(place Q1 10000 {ylo} front 0) (place Q2 10000 {yhi} front 0)
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(place Q3 10000 -1000 front 0) (place Q4 10000 -9000 front 0)))
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(library (image S (pin pad 1 0 0)) (padstack pad (shape (rect F.Cu -600 -600 600 600)) (attach off)))
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(network (net PWR (pins P1-1 P2-1)) (net SIG (pins Q1-1 Q3-1)) (net SIG2 (pins Q2-1 Q4-1))
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(class Power PWR (rule (width 500) (clearance 250)))))"""
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@pytest.mark.parametrize("resolution", [1, 2])
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@pytest.mark.parametrize("gap", [900, 1000, 1075])
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def test_a_wide_net_past_pads_it_does_not_fit_between_is_not_refused(gap, resolution):
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# 0.3 mm fits the gap between the two pads, 0.5 mm does not: the grid
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# must see that, rather than lay it wide and have the exact check drop it
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ylo, yhi = -5000 - gap // 2 - 600, -5000 + gap // 2 + 600
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result = build_exact_routing_result(
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parse_dsn(_WIDE.format(ylo=ylo, yhi=yhi)), resolution=resolution
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)
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assert result.unrouted == []
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def _wide_router():
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dsn = parse_dsn(_WIDE.format(ylo=-6050, yhi=-3950))
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s = dsn.resolution.value
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pwr = next(i for i, net in enumerate(dsn.nets, 1) if net.name == "PWR")
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return GridRouter(
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build_board(dsn),
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trace_width=round(_rule_width_dsn(dsn) * s),
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clearance=round(_rule_clearance_dsn(dsn) * s),
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resolution=2,
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net_widths={pwr: 5000},
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), pwr
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def test_a_wide_trace_keeps_clear_of_a_default_one_at_the_grid_diagonal():
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router, _pwr = _wide_router()
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# 0.5 mm against 0.3 mm needs 0.25 + 0.25 + 0.15 = 0.65 mm between centres,
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# on either axis, since the exact check compares boxes
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need = 2500 + router.clearance + router.half_width
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for dx, dy in [(2, 2), (2, 1), (1, 2)]:
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assert max(dx, dy) * router.step < need
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assert (dx, dy) in router._halo_for(2500)
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def test_a_wide_rip_up_route_counts_what_its_extra_width_crosses():
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router, pwr_net = _wide_router()
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conns = router._conns = router._build_connections()
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pwr = next(c for c in conns if c.net_no == pwr_net)
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other = next(c for c in conns if c.net_no != pwr_net)
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# a default-width trace two cells from the wide route's path
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x, y = 20, 5
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router._commit(other, _line((x - 3, y + 2), (x + 3, y + 2), 0))
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path = _line((x - 3, y), (x + 3, y), 0)
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spread = router._spread_for(2500)
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assert other.index not in router._crossed_owners(path, pwr.net_no, conns)
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assert other.index in router._crossed_owners(path, pwr.net_no, conns, spread)
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def test_a_pad_cell_check_uses_the_rotated_outline():
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board = build_board(parse_dsn(_socket_dsn(60, "y")))
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router = GridRouter(board, trace_width=3000, clearance=2500, resolution=2)
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oval = next(p for p in board.get_pins() if p.component_ref == "P3" and p.name == "2")
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box = oval.shape.bounding_box()
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margin = router.clearance + router.half_width
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exact = set(router._pad_cells(oval.shape, box, margin))
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boxed = set(router._cells_in_box(box, margin))
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assert exact < boxed
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for cell in boxed - exact:
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c = router._cell_center(cell)
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square = IntBox(c.x - margin, c.y - margin, c.x + margin, c.y + margin)
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assert oval.shape.intersection(square).dimension() != 2
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