Ryan Malloy
c2197f6fe6
Three-pass optimization eliminates cable crossings: 1. Order boundary components by average header pin position 2. Regroup header pins by boundary component (reduces inter-cable crossings) 3. Reorder boundary component pins to parallel header (eliminates within-cable crossings) Safety hardening from Apollo review: - Duplicate header pin deduplication (prevents silent mapping corruption) - Connection structure validation at entry - Fan-out averaging for component pins connected to multiple header pins - Explicit ValueError on pin remapping failures with diagnostic context 145 tests passing (was 130).
68 lines
1.0 KiB
YAML
68 lines
1.0 KiB
YAML
metadata:
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title: 'Wiring diagram: simple_board'
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source: tests/fixtures/simple_board.net
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generator: spice2wireviz 2026.2.13
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connectors:
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amplifier_board:
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type: Module Interface
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pinlabels:
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- VIN
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- GND
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- VOUT
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- SIGNAL_IN
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notes: 'SPICE subcircuit: .subckt amplifier_board'
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J1:
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type: PWR_CONN
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pinlabels:
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- VIN
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- GND
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notes: 'SPICE ref: J1, nets: VIN, GND'
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J2:
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type: SIG_CONN
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pinlabels:
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- VOUT
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- SIGNAL_IN
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notes: 'SPICE ref: J2, nets: SIGNAL_IN, VOUT'
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TP1:
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type: TP
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style: simple
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pinlabels:
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- N001
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notes: 'SPICE ref: TP1, nets: N001'
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cables:
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W_J1:
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category: bundle
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colors:
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- ''
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- BK
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wirelabels:
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- VIN
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- GND
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notes: 'Nets: VIN, GND'
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W_J2:
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category: bundle
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wirecount: 2
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wirelabels:
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- VOUT
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- SIGNAL_IN
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notes: 'Nets: VOUT, SIGNAL_IN'
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connections:
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- - amplifier_board:
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- 1
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- 2
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- W_J1:
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- 1
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- 2
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- J1:
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- 1
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- 2
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- - amplifier_board:
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- 3
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- 4
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- W_J2:
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- 1
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- 2
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- J2:
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- 1
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- 2
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