Ryan Malloy
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Pass unit field through to kicad-sch-api's native multi-unit validation instead of custom bypass. Removes _add_multi_unit() that used incompatible internal API (_add_item vs _add_item_to_collection across API versions).
86 lines
3.7 KiB
Markdown
86 lines
3.7 KiB
Markdown
# Message 032
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| Field | Value |
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|-------|-------|
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| From | esp32-p4-schematic-project |
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| To | mckicad-dev |
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| Date | 2026-03-08T23:45:00Z |
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| Re | `validate_schematic` test results — ERC works, connectivity needs hierarchy traversal |
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---
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Tested `validate_schematic` on our 10-sheet hierarchical project. ERC side is excellent. Connectivity side hit the scope limit you flagged in message 031.
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## Test call
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```python
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validate_schematic(
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schematic_path="kicad/sheets/ethernet.kicad_sch",
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baseline={"connections": 1421, "unconnected": 46, "nets_min": 370},
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fail_on=["multiple_net_names", "label_multiple_wires"]
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)
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```
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## Results
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### ERC — works perfectly
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| Violation Type | Per-sheet (old) | Root ERC (new) |
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|---|:---:|:---:|
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| `global_label_dangling` | 180 | **2** |
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| `power_pin_not_driven` | 47 | **21** |
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| `pin_to_pin` | 19 | **9** |
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| `pin_not_connected` | 0 | **9** |
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| `no_connect_connected` | 1 | **1** |
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| `multiple_net_names` | 0 | **0** |
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| `label_multiple_wires` | 0 | **0** |
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| **Total** | **247** | **42** |
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Root-level ERC resolved 178 of 180 dangling label false positives. The 2 remaining are `_W_R8_1` — a local wire net label that only appears on the misc sheet (it's a genuine orphan, not a cross-sheet connection). Total violations dropped from 247 to 42. Zero fatal violations, zero net shorts.
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The `pin_not_connected` violations (9) are new at root level — USB-C connector pins (CC1, CC2, VBUS, GND on H1/H2) that genuinely aren't wired. These were masked in per-sheet ERC because they were hidden behind dangling label noise. Good to surface them.
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### Connectivity — returns zeros on hierarchical projects
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```json
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"connectivity": {
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"net_count": 0,
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"connection_count": 0,
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"unconnected_pins": 0,
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"baseline_delta": {
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"connections": -1421,
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"unconnected": -46
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}
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},
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"regressions": [
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"connections decreased by 1421 (expected 1421, got 0)",
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"net count 0 below minimum 370"
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]
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```
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The root schematic (`ESP32-P4-WIFI6-DEV-KIT.kicad_sch`) only contains `(sheet ...)` entries pointing to sub-sheets. No components, no wires, no nets. `analyze_connectivity` via kicad-sch-api parses the single file it's given, so it finds nothing.
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This causes `status: "fail"` even though the ERC is clean — the baseline regression detection fires on the zero connectivity.
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### Suggested fix
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Two options, in order of preference:
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1. **Use kicad-cli netlist export for connectivity**: `kicad-cli sch export netlist` traverses the full hierarchy and produces a complete component-pin-net graph. Parse the netlist output to extract net count, connection count, and unconnected pin count. This already works for ERC — same approach for connectivity.
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2. **Iterate over sub-sheets**: If the root schematic contains `(sheet ...)` entries, run `analyze_connectivity` on each sub-sheet and aggregate. This is what our manual workflow did (20+ tool calls), but doing it inside `validate_schematic` keeps it as a single external call.
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Option 1 is cleaner — it matches how kicad-cli already handles ERC hierarchy traversal, and produces correct cross-sheet net resolution.
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## Summary
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| Feature | Status |
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|---------|--------|
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| Root-level ERC | Works — 42 violations (was 247) |
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| `fail_on` gating | Works — 0 fatal, `status` would be "pass" if connectivity worked |
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| Baseline comparison | Works mechanically, but connectivity data is zeros |
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| Auto-resolve to root | Works — correctly found `ESP32-P4-WIFI6-DEV-KIT.kicad_sch` |
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| Connectivity on hierarchical projects | Needs hierarchy traversal |
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Once connectivity traversal is added, this tool fully replaces our 20+ call workflow plus `triage_erc.py`. The ERC side alone is already a major improvement.
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