Rip every user of a shared via, and judge vias round at the outline

Two connections of a net can share a via. The grid kept one owner per via
cell next to the claim list, and the search and rip-up read only that owner:
a route of another net through the via ripped the first user and left the
second's via under the new trace. The exact check then threw one of them
out. The search and rip-up now read the claim list, and the single owner is
gone.

The exact check also tested a via against the outline as its square box,
whose corner reaches past a 45-degree chamfer where the round via does not.
The grid keeps the via's centre its radius plus the edge clearance from the
outline, as KiCad measures it; the exact check now does the same.

kitspace_minisumo_v3 seed 4: 4 rejected connections to 0, 11 failed to 7.

bench/diagnose.py

@@ -32,8 +32,10 @@ from freeroute.route.exact_router import route_board_exact
 from freeroute.route.grid_router import GridRouter, _ends_of
 from freeroute.route.pipeline import (
     _mm_to_board,
+    _net_widths_board,
     _rule_clearance_dsn,
     _rule_width_dsn,
+    _via_drill_board,
     _via_half_board,
 )
 
@@ -106,6 +108,15 @@ def _capture_conflicts() -> list:
     return log
 
 
+def _wall_name(wall, names) -> str:
+    if isinstance(wall, str):
+        if wall.startswith("fixed copper of net "):
+            net = int(wall.rsplit(" ", 1)[1])
+            return f"fixed copper of {names.get(net, net)}"
+        return wall
+    return names.get(wall, "pads/keepouts")
+
+
 def _gap(a, b) -> int:
     dx = max(b.ll.x - a.ur.x, a.ll.x - b.ur.x, 0)
     dy = max(b.ll.y - a.ur.y, a.ll.y - b.ur.y, 0)
@@ -118,6 +129,25 @@ def _fresh(seen) -> GridRouter:
     return router
 
 
+def _static_wall(router: GridRouter, node) -> str:
+    """What static copper closes a node: a keepout, copper already on the
+    board (a fixed via or track, by net), or a pad."""
+    if node in router._keepout:
+        return "keepout"
+    fixed = getattr(router, "_diag_fixed", None)
+    if fixed is None:
+        fixed = router._diag_fixed = {}
+        margin = router.clearance + router.half_width
+        for net, layers, box in router.board.get_fixed_copper():
+            for cell in router._cells_in_box(box, margin):
+                for layer in layers:
+                    fixed[(*cell, layer)] = net
+    net = fixed.get(node)
+    if net is not None:
+        return f"fixed copper of net {net}"
+    return "pads"
+
+
 def _flood(router: GridRouter, pin, net_no: int, conns) -> tuple[int, Counter]:
     """How many nodes a pin can reach through free cells (up to FLOOD_LIMIT),
     and which other nets' copper bounds the region."""
@@ -146,7 +176,7 @@ def _flood(router: GridRouter, pin, net_no: int, conns) -> tuple[int, Counter]:
                 for owner in owners:
                     walls[conns[owner].net_no] += 1
                 if not owners:
-                    walls[0] += 1  # a pad or keepout
+                    walls[_static_wall(router, n)] += 1
                 continue
             seen.add(n)
             frontier.append(n)
@@ -155,7 +185,7 @@ def _flood(router: GridRouter, pin, net_no: int, conns) -> tuple[int, Counter]:
 
 def diagnose(
     dsn_text: str, edge_clearance_mm: float | None, resolution: int = 2, shove: bool = False,
-    access_cost: float = 0.0,
+    access_cost: float = 0.0, hole_to_hole_mm: float = 0.25, seed: int | None = None,
 ) -> dict:
     dsn = parse_dsn(dsn_text)
     names = {i + 1: n.name for i, n in enumerate(dsn.nets)}
@@ -171,6 +201,11 @@ def diagnose(
         resolution=resolution,
         shove=shove,
         access_cost=access_cost,
+        seed=seed,
+        # the product's configuration: net-class widths and hole spacing
+        net_widths=_net_widths_board(dsn, scale),
+        via_drill=_via_drill_board(dsn, scale),
+        hole_to_hole=_mm_to_board(dsn, scale, hole_to_hole_mm) or 0,
     )
     routed = seen["router"]
     best = routed._diag_best
@@ -224,7 +259,9 @@ def diagnose(
                     if reach < FLOOD_LIMIT:
                         walled.append({
                             "pin": end, "reach": reach,
-                            "walls": [names.get(n, "pads/keepouts") for n, _ in walls.most_common(4)],
+                            "walls": [
+                                _wall_name(n, names) for n, _ in walls.most_common(4)
+                            ],
                         })
             row["kind"] = "walled-in" if walled else "congestion"
             if walled:
@@ -240,11 +277,13 @@ def main(argv: list[str] | None = None) -> int:
     ap.add_argument("--grid-resolution", type=int, default=2, metavar="K")
     ap.add_argument("--shove", action="store_true", help="as mckicad routes")
     ap.add_argument("--access-cost", type=float, default=0.0)
+    ap.add_argument("--seed", type=int, help="route in this shuffled order, as bench.py does")
+    ap.add_argument("--hole-to-hole", type=float, default=0.25, metavar="MM")
     ap.add_argument("--json", type=Path, help="also write the full table here")
     args = ap.parse_args(argv)
 
     report = diagnose(args.dsn.read_text(), args.edge_clearance, args.grid_resolution, args.shove,
-                      args.access_cost)
+                      args.access_cost, args.hole_to_hole, args.seed)
     for row in report["failures"]:
         extra = ""
         for w in row.get("walled", []):

bench/drc_check.sh

@@ -0,0 +1,67 @@
+#!/usr/bin/env bash
+# Route one KiCad board with freeroute and judge the result with KiCad's DRC.
+#
+#   bench/drc_check.sh [--keep] <board.kicad_pcb> <out-dir> [freeroute args...]
+#
+# Copies the board (and its .kicad_pro) into <out-dir>, strips its tracks and
+# vias unless --keep is given (then they reach the router as fixed wiring),
+# exports the DSN through mckicad, routes, applies the session, and runs DRC
+# with zones refilled at every severity. Prints one line: time, copper added,
+# shorts, opens, hole problems (whatever severity the board gives them) and
+# the other errors. The source board is never touched.
+#
+# FREEROUTE (default: this checkout's .venv/bin/freeroute) and MCK (default
+# ~/claude/mckicad) pick the builds to judge.
+set -euo pipefail
+keep=0
+if [[ "${1:-}" == "--keep" ]]; then keep=1; shift; fi
+src="$1"; out="$2"; shift 2
+here="$(cd "$(dirname "$0")/.." && pwd)"
+FREEROUTE="${FREEROUTE:-$here/.venv/bin/freeroute}"
+MCK="${MCK:-$HOME/claude/mckicad}"
+rm -rf "$out"; mkdir -p "$out"
+cp "${src%.kicad_pcb}.kicad_pro" "$out/board.kicad_pro" 2>/dev/null || true
+
+if [[ $keep == 1 ]]; then
+    cp "$src" "$out/board.kicad_pcb"
+else
+    (cd "$MCK" && uv run --no-sync python - "$src" "$out/board.kicad_pcb" <<'EOF'
+import sys
+from mckicad.utils.sexp_tree import parse
+text = open(sys.argv[1]).read()
+spans = sorted((c.span for c in parse(text).children if c.tag in ("segment", "arc", "via")), reverse=True)
+for a, b in spans:
+    text = text[:a] + text[b:]
+open(sys.argv[2], "w").write(text)
+EOF
+    )
+fi
+
+(cd "$MCK" && uv run --no-sync python -c "
+from mckicad.utils.freerouting import FreeRoutingEngine
+assert FreeRoutingEngine().export_dsn_from_kicad('$out/board.kicad_pcb', '$out/board.dsn', {})") \
+    >/dev/null 2>&1 || { echo "$out: DSN export failed"; exit 1; }
+
+start=$(date +%s.%N)
+"$FREEROUTE" "$out/board.dsn" -do "$out/board.ses" "$@" >"$out/route.log" 2>&1 || true
+secs=$(python3 -c "print(round($(date +%s.%N)-$start,1))")
+[[ -s "$out/board.ses" ]] || { echo "$out: no session ($(tail -1 "$out/route.log"))"; exit 1; }
+
+(cd "$MCK" && uv run --no-sync python -c "
+from mckicad.utils.ses_apply import apply_ses_to_board as a
+r = a('$out/board.kicad_pcb', '$out/board.ses', '$out/board.kicad_pcb')
+print(r['segments_added'], r['vias_added'])" 2>/dev/null) >"$out/apply.txt"
+
+kicad-cli pcb drc --refill-zones --format json --severity-all \
+    -o "$out/drc.json" "$out/board.kicad_pcb" >/dev/null 2>&1 || true
+python3 - "$out" "$secs" <<'EOF'
+import collections, json, sys
+out, secs = sys.argv[1:]
+seg, via = open(f"{out}/apply.txt").read().split()
+d = json.load(open(f"{out}/drc.json"))
+errors = collections.Counter(v["type"] for v in d["violations"] if v.get("severity") == "error")
+other = collections.Counter(v["type"] for v in d["violations"] if v.get("severity") != "error")
+holes = {k: errors.pop(k, 0) + other.get(k, 0) for k in ("holes_co_located", "hole_to_hole")}
+print(f"{out}: {secs}s  {seg} seg {via} via  shorts {errors.pop('shorting_items', 0)}  "
+      f"opens {len(d.get('unconnected_items', []))}  holes {holes}  errors {dict(errors)}")
+EOF

src/freeroute/board/build.py

@@ -12,9 +12,10 @@ model. It mirrors what FreeRouting's ``Structure.create_board`` / ``Library`` /
 * padstacks x placement -> :class:`Pin` items
 * keepouts -> :class:`ObstacleArea` items
 
-Pad geometry: a rectangle pad becomes an exact :class:`IntBox`; a circle pad its
-bounding box (documented approximation pending an exact circle tile); a convex
-polygon pad an exact :class:`Simplex`. Every pad is placed centred on its pin
+Pad geometry: a rectangle pad becomes an exact :class:`IntBox`; a circle pad a
+16-sided :class:`Simplex` drawn just outside it (its corners stand out by 2% of
+the radius, where the bounding box's stood out by 41%); a convex polygon pad an
+exact :class:`Simplex`. Every pad is placed centred on its pin
 location, so it contains that location by construction. Component rotation is
 applied to the pin position; the pad tile itself is not rotated (irrelevant to
 the containment invariant, and pads are centre-symmetric in practice).
@@ -23,6 +24,7 @@ the containment invariant, and pads are centre-symmetric in practice).
 from __future__ import annotations
 
 import math
+import re
 
 from freeroute.dsn.model import DsnBoard
 from freeroute.dsn.shapes import Circle, Path, Polygon, Rectangle, Shape
@@ -38,6 +40,9 @@ from .transform import CoordinateTransform
 
 __all__ = ["build_board"]
 
+# DSN units per micrometre, for drills KiCad gives in um in via padstack names
+_DSN_PER_UM = {"um": 1.0, "mm": 0.001, "mil": 1 / 25.4, "inch": 1 / 25400}
+
 
 def build_board(dsn: DsnBoard) -> BasicBoard:
     """Construct a :class:`BasicBoard` from a parsed :class:`DsnBoard`."""
@@ -245,7 +250,7 @@ def _placed_pad_tile(shape: Shape, place, dsn_pin, transform: CoordinateTransfor
         r = round(transform.dsn_to_board(shape.diameter / 2))
         cx = round(transform.dsn_to_board(centre.x))
         cy = round(transform.dsn_to_board(centre.y))
-        return IntBox(cx - r, cy - r, cx + r, cy + r)
+        return _circle_tile(cx, cy, r)
     if isinstance(shape, Rectangle):
         x0, y0, x1, y1 = shape.coords[:4]
         corners = [(x0, y0), (x1, y0), (x1, y1), (x0, y1)]
@@ -264,15 +269,65 @@ def _placed_pad_tile(shape: Shape, place, dsn_pin, transform: CoordinateTransfor
     for x, y in corners:
         p = _to_board_offset(place, x, y, dsn_pin.rotation)
         pts.append(IntPoint(round(transform.dsn_to_board(p.x)), round(transform.dsn_to_board(p.y))))
-    if len(pts) >= 3:
-        simplex = Simplex.from_corners(pts)
-        if not simplex.is_empty():
-            return simplex
+    # An oval's padded corners are not in outline order, and a mirrored
+    # part reverses the winding: take the convex hull, then either winding.
+    hull = _convex_hull(pts)
+    if len(hull) >= 3:
+        for corners in (hull, hull[::-1]):
+            simplex = Simplex.from_corners(corners)
+            if not simplex.is_empty():
+                return simplex
     xs = [p.x for p in pts] or [0]
     ys = [p.y for p in pts] or [0]
     return IntBox(min(xs), min(ys), max(xs), max(ys))
 
 
+_CIRCLE_SIDES = 16
+
+
+def _circle_tile(cx: int, cy: int, r: int):
+    """A polygon around the circle, every side touching it. A square around a
+    big round pad (a mounting hole) puts phantom copper in its corners that
+    blocks legal routes past it; this stays outside the circle, so the router
+    is still never closer than KiCad measures."""
+    if r < 8:
+        return IntBox(cx - r, cy - r, cx + r, cy + r)
+    reach = r / math.cos(math.pi / _CIRCLE_SIDES)
+    corners = []
+    for k in range(_CIRCLE_SIDES):
+        a = (k + 0.5) * 2 * math.pi / _CIRCLE_SIDES
+        dx, dy = reach * math.cos(a), reach * math.sin(a)
+        # round away from the centre so the polygon never cuts into the circle
+        corners.append(IntPoint(cx + math.copysign(math.ceil(abs(dx)), dx),
+                                cy + math.copysign(math.ceil(abs(dy)), dy)))
+    corners = [IntPoint(int(p.x), int(p.y)) for p in corners]
+    for winding in (corners, corners[::-1]):
+        simplex = Simplex.from_corners(winding)
+        if not simplex.is_empty():
+            return simplex
+    return IntBox(cx - r, cy - r, cx + r, cy + r)
+
+
+def _convex_hull(pts: list[IntPoint]) -> list[IntPoint]:
+    """The convex hull of ``pts`` counter-clockwise, collinear points dropped."""
+    ps = sorted({(p.x, p.y) for p in pts})
+    if len(ps) < 3:
+        return [IntPoint(x, y) for x, y in ps]
+
+    def cross(o, a, b):
+        return (a[0] - o[0]) * (b[1] - o[1]) - (a[1] - o[1]) * (b[0] - o[0])
+
+    def half(points):
+        out: list[tuple[int, int]] = []
+        for p in points:
+            while len(out) >= 2 and cross(out[-2], out[-1], p) <= 0:
+                out.pop()
+            out.append(p)
+        return out[:-1]
+
+    return [IntPoint(x, y) for x, y in half(ps) + half(ps[::-1])]
+
+
 def _pad_tile(shape: Shape, transform: CoordinateTransform):
     """A board-relative pad tile from a DSN padstack shape (centred near origin)."""
     if isinstance(shape, Rectangle):
@@ -282,7 +337,7 @@ def _pad_tile(shape: Shape, transform: CoordinateTransform):
         r = round(transform.dsn_to_board(shape.diameter / 2))
         cx = round(transform.dsn_to_board(shape.center_x))
         cy = round(transform.dsn_to_board(shape.center_y))
-        return IntBox(cx - r, cy - r, cx + r, cy + r)  # bounding-box approximation
+        return _circle_tile(cx, cy, r)
     if isinstance(shape, (Polygon, Path)):
         coords = shape.coords
         pts = [
@@ -503,10 +558,15 @@ def _insert_wiring(dsn: DsnBoard, board: BasicBoard, transform: CoordinateTransf
         location = transform.dsn_to_board_point(via.x, via.y)
         pad = _pad_tile(max(padstack.shapes, key=_shape_extent), transform)
         box = pad.bounding_box()
+        drill = re.search(r"_([\d.]+):([\d.]+)_um", via.padstack)
+        drill_board = (
+            round(transform.dsn_to_board(float(drill.group(2)) * _DSN_PER_UM.get(dsn.unit, 1.0)))
+            if drill else 0
+        )
         board.insert(
             Via(
                 net_nos=[numbers[via.net]], fixed=True, padstack_name=via.padstack,
-                location=location, layers=sorted(layers or signal_layers),
+                drill=drill_board, location=location, layers=sorted(layers or signal_layers),
                 shape=IntBox(box.ll.x + location.x, box.ll.y + location.y,
                              box.ur.x + location.x, box.ur.y + location.y),
             )

src/freeroute/board/items.py

@@ -117,6 +117,8 @@ class Via(Item):
     #: layer indices the via's pads occupy, and the largest pad as a box
     layers: list[int] = field(default_factory=list)
     shape: object = None
+    #: drill diameter in board units, when the padstack name gives it
+    drill: int = 0
 
 
 @dataclass

src/freeroute/board/search_tree.py

@@ -188,6 +188,8 @@ class ShapeSearchTree:
         overlap). Static pad-vs-pad spacing in the source design is not counted.
         """
         for shape in self.all_shapes():
+            if not shape.routed:
+                continue  # a pair with routed copper is checked from that side
             expanded = shape.tile.offset(clearance)
             grown = None  # exact clearance region, built lazily only for diagonals
             for other in self.overlapping(expanded):

src/freeroute/cli.py

@@ -175,6 +175,14 @@ def build_parser() -> argparse.ArgumentParser:
         "connections a rip-up displaces are rerouted at once and the rip-up is undone "
         "if fewer connections end up routed",
     )
+    parser.add_argument(
+        "--hole-to-hole",
+        type=float,
+        default=0.25,
+        metavar="MM",
+        help="grid and exact engines: least distance between the edges of any two via "
+        "holes, of one net or two (KiCad's min_hole_to_hole; default 0.25)",
+    )
     parser.add_argument(
         "--jobs",
         type=int,
@@ -239,6 +247,7 @@ def main(argv: list[str] | None = None) -> int:
             "resolution": 2 if args.grid_resolution is None else args.grid_resolution,
             "heuristic_weight": args.heuristic_weight,
             "access_cost": args.access_cost or 0.0,
+            "hole_to_hole_mm": args.hole_to_hole,
             "rollback": args.rollback,
         }
     elif args.engine == "grid":
@@ -249,6 +258,7 @@ def main(argv: list[str] | None = None) -> int:
             "edge_clearance_mm": args.edge_clearance,
             "resolution": 1 if args.grid_resolution is None else args.grid_resolution,
             "access_cost": args.access_cost or 0.0,
+            "hole_to_hole_mm": args.hole_to_hole,
             "rollback": args.rollback,
         }
     if args.engine == "room":
@@ -287,6 +297,14 @@ def main(argv: list[str] | None = None) -> int:
         print(f"freeroute: {len(missing)} connection(s) not routed:", file=sys.stderr)
         for net, a, b, _zone in missing:
             print(f"  {net}: {a} to {b}", file=sys.stderr)
+    if result.narrowed:
+        print(
+            f"freeroute: {len(result.narrowed)} connection(s) of a wider net class only fitted "
+            "at the default width; their nets are written at the default width:",
+            file=sys.stderr,
+        )
+        for net, a, b in result.narrowed:
+            print(f"  {net}: {a} to {b}", file=sys.stderr)
     if in_zone:
         print(
             f"freeroute: {len(in_zone)} more connection(s) left to a zone fill that may join them:",

src/freeroute/route/exact_router.py

@@ -31,13 +31,14 @@ from dataclasses import dataclass, field
 import math
 
 from freeroute.board.board import BasicBoard
-from freeroute.board.items import Pin
+from freeroute.board.items import Pin, Via
 from freeroute.board.search_tree import ShapeSearchTree, TreeShape
 from freeroute.geometry import (
     IntBox,
     IntPoint,
     Polyline,
     PolylineShape,
+    Simplex,
     segment_box,
     segment_octagon,
     shove_segment,
@@ -99,6 +100,9 @@ def route_board_exact(
     route_first: frozenset | None = None,
     access_cost: float = 0.0,
     rollback: bool = True,
+    net_widths: dict[int, int] | None = None,
+    via_drill: int | None = None,
+    hole_to_hole: int = 0,
 ) -> ExactRouteResult:
     """Route ``board`` orthogonally and verify the result with exact geometry.
 
@@ -131,6 +135,9 @@ def route_board_exact(
         route_first=route_first,
         access_cost=access_cost,
         rollback=rollback,
+        net_widths=net_widths,
+        via_drill=via_drill,
+        hole_to_hole=hole_to_hole,
     )
     edge = 0 if edge_clearance is None else edge_clearance
     outline = board.outline
@@ -148,7 +155,9 @@ def route_board_exact(
         net = pin.net_nos[0] if pin.net_nos else -1
         pin_layers = frozenset(layer for layer in pin.layers if layer in signal_layers)
         if pin_layers:
-            tree.insert(TreeShape(next(owner), net, pin_layers, box))
+            # a rotated pad is checked against its outline, not its box
+            exact = pin.shape if _is_rotated(pin.shape) else None
+            tree.insert(TreeShape(next(owner), net, pin_layers, box, exact=exact))
     for net, copper_layers, box in board.get_fixed_copper():
         on = frozenset(layer for layer in copper_layers if layer in signal_layers)
         if on and not box.is_empty():
@@ -172,24 +181,35 @@ def route_board_exact(
 
     via_layers = frozenset(signal_layers)
     accepted: dict[int, _Accepted] = {}
+    fixed_vias = {
+        (item.net_nos[0], item.location)
+        for item in board.get_items()
+        if isinstance(item, Via) and item.fixed and item.net_nos
+    }
 
     # Verify connection by connection, so one conflicting segment of a
     # 25-pin supply net costs that one connection, not the whole net.
     rejected: list[tuple[int, str, str]] = []
     ends_list = result.connection_ends or [("?", "?", "")] * len(result.connections)
+    # each net is checked at the width it will be written at: its class's
+    # when all of its connections went in at that, else the default
+    net_half = dict(result.net_half)
     for (net_no, wires, vias), ends in sorted(
         zip(result.connections, ends_list, strict=False), key=lambda c: c[0][0]
     ):
-        boxes = _copper_boxes(wires, vias, half_width, via_layers, via_half)
-        wire_count = len(_copper_boxes(wires, [], half_width, via_layers, via_half))
+        wire_half = net_half.get(net_no, half_width)
+        boxes = _copper_boxes(wires, vias, wire_half, via_layers, via_half)
+        wire_count = len(_copper_boxes(wires, [], wire_half, via_layers, via_half))
         if any(
             tree.clearance_conflict(
                 box, net_no, layer, clearance, "wire" if i < wire_count else "via"
             )
             for i, (box, box_layers) in enumerate(boxes)
             for layer in box_layers
-        ) or _end_in_rule_area(tree, wires, half_width) or (
-            outline is not None and not all(outline.box_clear(b, edge) for b, _ in boxes)
+        ) or _end_in_rule_area(tree, wires, wire_half) or (
+            outline is not None and not _inside_outline(
+                outline, boxes[:wire_count], vias, (via_half or wire_half) + edge, edge
+            )
         ):
             rejected.append((net_no, *ends))
             continue  # exact-clearance conflict -> drop (may be recovered by shove)
@@ -197,7 +217,12 @@ def route_board_exact(
         if acc is None:
             acc = accepted[net_no] = _Accepted(wires=[], vias=[])
         acc.wires.extend(wires)
-        acc.vias.extend(vias)
+        # connections of one net that end on the same plane cell share its
+        # via: write it once, and never on top of a via already on the board
+        acc.vias.extend(
+            v for v in dict.fromkeys(vias)
+            if v not in acc.vias and not _on_fixed_via(net_no, v, fixed_vias, via_half)
+        )
         for box, box_layers in boxes:
             oid = next(owner)
             tree.insert(TreeShape(oid, net_no, box_layers, box, routed=True))
@@ -247,6 +272,17 @@ def route_board_exact(
     for net_no, acc in accepted.items():
         clean.wires[net_no] = acc.wires
         clean.vias[net_no] = acc.vias
+    # shove and the diagonal pass lay copper at the default width: nets they
+    # recovered, and nets whose traces shove pushed aside
+    reshaped = (set(accepted) - accepted_before_recovery) | {
+        net for net, acc in accepted.items() if acc.shove_count
+    }
+    if diagonal:
+        reshaped = set(accepted)
+    clean.net_half = {
+        net: half for net, half in net_half.items() if net in accepted and net not in reshaped
+    }
+    clean.narrowed = list(result.narrowed)
 
     drc_clean = tree.has_violation(clearance) is None
     return ExactRouteResult(result=clean, tree=tree, drc_clean=drc_clean, shoves=shoves)
@@ -615,6 +651,15 @@ def _end_in_rule_area(tree, wires, half_width) -> bool:
     return False
 
 
+def _on_fixed_via(net_no, point, fixed_vias, via_half) -> bool:
+    """A routed via that reuses a via already on the board: the grid put it
+    on the fixed via's cell, a little off its centre, and it is not written."""
+    return any(
+        net == net_no and abs(loc.x - point.x) <= via_half and abs(loc.y - point.y) <= via_half
+        for net, loc in fixed_vias
+    )
+
+
 def _copper_boxes(wires, vias, half_width, via_layers, via_half=None):
     via_half = via_half or half_width
     boxes: list[tuple[IntBox, frozenset[int]]] = []
@@ -627,6 +672,19 @@ def _copper_boxes(wires, vias, half_width, via_layers, via_half=None):
     return boxes
 
 
+def _inside_outline(outline, wire_boxes, vias, via_reach, edge) -> bool:
+    """Copper inside the board, ``edge`` from its outline. A via is round, as
+    the grid and KiCad take it: its square box would reach past a chamfered
+    corner where the via itself does not."""
+    return all(outline.box_clear(b, edge) for b, _ in wire_boxes) and all(
+        outline.point_clear(v, via_reach) for v in vias
+    )
+
+
+def _is_rotated(shape) -> bool:
+    return isinstance(shape, Simplex) and not shape.is_int_box()
+
+
 def _net_pins(board: BasicBoard, net_no: int, signal_layers) -> list[Pin]:
     return [
         pin

src/freeroute/route/pipeline.py

@@ -12,6 +12,8 @@ to DSN units (dividing by the resolution) for the SES ``(wire (path ...))`` and
 
 from __future__ import annotations
 
+import re
+
 from freeroute.board import build_board
 from freeroute.dsn import DsnBoard, parse_dsn
 from freeroute.ses import RoutedVia, RoutedWire, RoutingResult, write_ses
@@ -34,6 +36,25 @@ def _rule_width_dsn(dsn: DsnBoard) -> float:
     return rules[0].value if rules else _DEFAULT_WIDTH_DSN
 
 
+def _net_widths_board(dsn: DsnBoard, scale: int) -> dict[int, int]:
+    """Track width of every net whose class asks for more than the default,
+    in board units, by net number (build_board numbers nets in DSN order)."""
+    default = _rule_width_dsn(dsn)
+    by_name: dict[str, float] = {}
+    for net_class in dsn.net_classes:
+        if not net_class.width_rules:
+            continue
+        width = net_class.width_rules[0].value
+        if width > default:
+            for name in net_class.net_names:
+                by_name[name] = max(by_name.get(name, 0.0), width)
+    return {
+        i + 1: round(by_name[net.name] * scale)
+        for i, net in enumerate(dsn.nets)
+        if net.name in by_name
+    }
+
+
 def _rule_clearance_dsn(dsn: DsnBoard) -> float:
     for rule in dsn.structure_rules.clearance_rules:
         if not rule.class_pairs:  # the layer-wide default clearance
@@ -53,6 +74,20 @@ def _mm_to_board(dsn: DsnBoard, scale: int, value_mm: float | None) -> int | Non
     return round(value_mm / unit_mm * scale)
 
 
+def _via_drill_board(dsn: DsnBoard, scale: int) -> int | None:
+    """The via's drill in board units, from KiCad's padstack name
+    (``Via[0-1]_600:300_um`` is a 600 um pad with a 300 um drill); None when
+    the name does not say, and the pad size stands in for it."""
+    match = re.search(r"_([\d.]+):([\d.]+)_um", _via_padstack(dsn))
+    if not match:
+        return None
+    return round(float(match.group(2)) * _dsn_units_per_um(dsn) * scale)
+
+
+def _dsn_units_per_um(dsn: DsnBoard) -> float:
+    return {"um": 1.0, "mm": 0.001, "mil": 1 / 25.4, "inch": 1 / 25400}.get(dsn.unit, 1.0)
+
+
 def _via_half_board(dsn: DsnBoard, scale: int) -> int | None:
     """Half the via pad's size in board units, from the DSN's via padstack.
 
@@ -83,6 +118,7 @@ def route_dsn_board(
     seed: int | None = None,
     route_first: frozenset | None = None,
     access_cost: float = 0.0,
+    hole_to_hole_mm: float = 0.25,
     rollback: bool = True,
 ) -> tuple[RouteResult, int, list[str]]:
     """Route a parsed :class:`DsnBoard`; return the board-unit result, the scale,
@@ -108,6 +144,9 @@ def route_dsn_board(
         route_first=route_first,
         access_cost=access_cost,
         rollback=rollback,
+        net_widths=_net_widths_board(dsn, scale),
+        via_drill=_via_drill_board(dsn, scale),
+        hole_to_hole=_mm_to_board(dsn, scale, hole_to_hole_mm) or 0,
     )
     return result, scale, [layer.name for layer in dsn.layers]
 
@@ -122,6 +161,9 @@ def _to_routing_result(route, dsn: DsnBoard, scale: int, layer_names: list[str])
     result = RoutingResult()
     for net_no, segments in route.wires.items():
         name = numbers_to_names.get(net_no, str(net_no))
+        # its class's width when every connection of the net went in at it
+        half = getattr(route, "net_half", {}).get(net_no)
+        net_width = 2 * half / scale if half else width_dsn
         for layer_index, path in segments:
             layer_name = layer_names[layer_index] if layer_index < len(layer_names) else "F.Cu"
             coords: list[float] = []
@@ -129,7 +171,7 @@ def _to_routing_result(route, dsn: DsnBoard, scale: int, layer_names: list[str])
                 coords.append(point.x / scale)
                 coords.append(point.y / scale)
             if len(coords) >= 4:
-                result.add_wire(name, RoutedWire(layer=layer_name, width=width_dsn, coords=coords))
+                result.add_wire(name, RoutedWire(layer=layer_name, width=net_width, coords=coords))
     for net_no, locations in route.vias.items():
         name = numbers_to_names.get(net_no, str(net_no))
         for loc in locations:
@@ -137,6 +179,9 @@ def _to_routing_result(route, dsn: DsnBoard, scale: int, layer_names: list[str])
     result.unrouted = [
         (numbers_to_names.get(n, str(n)), a, b, zone) for n, a, b, zone in getattr(route, "failed", [])
     ]
+    result.narrowed = [
+        (numbers_to_names.get(n, str(n)), a, b) for n, a, b in getattr(route, "narrowed", [])
+    ]
     return result
 
 
@@ -151,6 +196,7 @@ def build_routing_result(
     seed: int | None = None,
     route_first: frozenset | None = None,
     access_cost: float = 0.0,
+    hole_to_hole_mm: float = 0.25,
     rollback: bool = True,
 ) -> RoutingResult:
     """Route ``dsn`` (grid track) and convert to a DSN-unit RoutingResult."""
@@ -159,6 +205,7 @@ def build_routing_result(
         edge_clearance_mm=edge_clearance_mm, resolution=resolution, seed=seed,
         route_first=route_first,
         access_cost=access_cost,
+        hole_to_hole_mm=hole_to_hole_mm,
         rollback=rollback,
     )
     return _to_routing_result(route, dsn, scale, layer_names)
@@ -178,6 +225,7 @@ def route_dsn_board_exact(
     seed: int | None = None,
     route_first: frozenset | None = None,
     access_cost: float = 0.0,
+    hole_to_hole_mm: float = 0.25,
     rollback: bool = True,
 ) -> tuple[ExactRouteResult, int, list[str]]:
     """Route a parsed :class:`DsnBoard` with the exact-geometry (orthogonal,
@@ -207,6 +255,9 @@ def route_dsn_board_exact(
         route_first=route_first,
         access_cost=access_cost,
         rollback=rollback,
+        net_widths=_net_widths_board(dsn, scale),
+        via_drill=_via_drill_board(dsn, scale),
+        hole_to_hole=_mm_to_board(dsn, scale, hole_to_hole_mm) or 0,
     )
     return exact, scale, [layer.name for layer in dsn.layers]
 
@@ -225,6 +276,7 @@ def build_exact_routing_result(
     seed: int | None = None,
     route_first: frozenset | None = None,
     access_cost: float = 0.0,
+    hole_to_hole_mm: float = 0.25,
     rollback: bool = True,
 ) -> RoutingResult:
     """Route ``dsn`` (exact track) and convert to a DSN-unit RoutingResult."""
@@ -241,6 +293,7 @@ def build_exact_routing_result(
         seed=seed,
         route_first=route_first,
         access_cost=access_cost,
+        hole_to_hole_mm=hole_to_hole_mm,
         rollback=rollback,
     )
     return _to_routing_result(exact.result, dsn, scale, layer_names)

src/freeroute/ses/model.py

@@ -60,6 +60,9 @@ class RoutingResult:
     #: connections the router could not make: (net name, one end, other end,
     #: the zone both ends sit in or "") -- a zone's fill may join the latter
     unrouted: list[tuple[str, str, str, str]] = field(default_factory=list)
+    #: connections of a wider net class that only fitted at the default width
+    #: (net name, one end, other end); their net is written at the default
+    narrowed: list[tuple[str, str, str]] = field(default_factory=list)
 
     def net(self, name: str, *, create: bool = False) -> RoutedNet | None:
         """Return the :class:`RoutedNet` with ``name`` (creating it if asked)."""

tests/route/test_fixed_wiring.py

@@ -48,3 +48,61 @@ def test_other_nets_route_around_a_fixed_track():
             continue
         for p, q in zip(pts, pts[1:], strict=False):
             assert not (min(p.x, q.x) < wall < max(p.x, q.x)), "crossed the GND track on F.Cu"
+
+
+# --- fixed wiring as connectivity ------------------------------------------
+
+_FANOUT = """(pcb fanout (parser) (resolution um 10) (unit um)
+  (structure
+    (layer F.Cu (type signal)) (layer In1.Cu (type power)) (layer In2.Cu (type power))
+    (layer B.Cu (type signal))
+    (boundary (path pcb 0  0 0  30000 0  30000 -20000  0 -20000  0 0))
+    (plane GND (polygon In1.Cu 0  500 -500  29500 -500  29500 -19500  500 -19500  500 -500))
+    (via "Via[0-3]_600:300_um") (rule (width 150) (clearance 150)))
+  (placement (component S (place G1 5000 -10000 front 0) (place A 10000 -10000 front 0)
+                          (place B 25000 -11500 back 0)))
+  (library
+    (image S (pin smd 1 0 0))
+    (padstack smd (shape (rect F.Cu -300 -300 300 300)) (attach off))
+    (padstack "Via[0-3]_600:300_um" (shape (circle F.Cu 600)) (shape (circle B.Cu 600)) (attach off)))
+  (network (net GND (pins G1-1)) (net SIG (pins A-1 B-1)))
+  (wiring
+    (wire (path F.Cu 150  5000 -10000  5000 -11500) (net GND) (type route))
+    (via "Via[0-3]_600:300_um"  5000 -11500 (net GND) (type route))
+    (wire (path F.Cu 150  10000 -10000  10000 -11500) (net SIG) (type route))
+    (via "Via[0-3]_600:300_um"  10000 -11500 (net SIG) (type route))
+    (wire (path F.Cu 300  2000 -2000  8000 -2000) (net GND) (type route))))"""
+
+
+def test_a_pad_fanned_out_to_its_plane_needs_no_route():
+    dsn = parse_dsn(_FANOUT)
+    exact, _scale, _names = route_dsn_board_exact(dsn, resolution=2)
+    gnd = next(i + 1 for i, n in enumerate(dsn.nets) if n.name == "GND")
+    assert exact.result.failed == []
+    assert not exact.result.vias.get(gnd) and not exact.result.wires.get(gnd)
+
+
+def test_a_fanned_out_signal_is_routed_from_its_via():
+    # B is on the bottom face, level with A's fan-out via: starting from that
+    # via on B.Cu is the cheapest way, and needs no via of its own
+    dsn = parse_dsn(_FANOUT)
+    exact, scale, names = route_dsn_board_exact(dsn, resolution=2)
+    sig = next(i + 1 for i, n in enumerate(dsn.nets) if n.name == "SIG")
+    assert sig in exact.result.routed_net_numbers
+    assert not exact.result.vias.get(sig), "the fan-out via is already there"
+    assert {names[layer] for layer, _ in exact.result.wires[sig]} == {"B.Cu"}
+
+
+def test_the_session_never_repeats_copper_already_on_the_board():
+    # the JAR writes the DSN's wiring back into its session, and an applier
+    # then adds it a second time on top of itself; freeroute writes only
+    # what it routed
+    from freeroute.route.pipeline import build_exact_routing_result
+
+    fixed_vias = {(5000.0, -11500.0), (10000.0, -11500.0)}
+    fixed_paths = {(5000.0, -10000.0, 5000.0, -11500.0), (10000.0, -10000.0, 10000.0, -11500.0),
+                   (2000.0, -2000.0, 8000.0, -2000.0)}
+    result = build_exact_routing_result(parse_dsn(_FANOUT), resolution=2)
+    for net in result.nets:
+        assert not {(v.x, v.y) for v in net.vias} & fixed_vias
+        assert not {tuple(w.coords) for w in net.wires} & fixed_paths

tests/route/test_grid_exact_agreement.py

@@ -0,0 +1,284 @@
+"""The grid must not believe copper legal that the exact check then refuses.
+
+Each case is one way the two used to disagree on roomba-ESP12E: a rotated oval
+pad modelled as an inflated box (and opened to its own net), a via shared by
+two connections of a net losing its footprint when one of them is ripped, and
+a wider net class searched as if it were the default width.
+"""
+
+from __future__ import annotations
+
+import math
+
+import pytest
+
+from freeroute.board import build_board
+from freeroute.dsn import parse_dsn
+from freeroute.geometry import IntBox, Simplex
+from freeroute.route.grid_router import GridRouter
+from freeroute.route.pipeline import (
+    _rule_clearance_dsn,
+    _rule_width_dsn,
+    _via_half_board,
+    build_exact_routing_result,
+)
+
+# --- rotated oval pads -------------------------------------------------------
+
+
+def _socket_dsn(rotation: float, layout: str) -> str:
+    """A 1x4 2.54 mm socket strip (rect pin 1, oval pins 2-4) at ``rotation``,
+    each pin its own net, routed to a small SMD pad 0.9 mm away."""
+    cx, cy = 100000, -100000
+    t = math.radians(rotation)
+    ax = (math.cos(t), math.sin(t))
+    perp = (-math.sin(t), math.cos(t))
+    places = []
+    for i in range(4):
+        px, py = cx + 2540 * i * ax[0], cy + 2540 * i * ax[1]
+        side = 1 if i % 2 == 0 else -1
+        if layout == "y":
+            tx, ty = px, py + side * 9000
+        else:
+            tx, ty = px + side * 8000 * perp[0], py + side * 8000 * perp[1]
+        places.append(f"(place T{i + 1} {round(tx)} {round(ty)} front 0)")
+    nets = " ".join(f"(net N{i} (pins P3-{i + 1} T{i + 1}-1))" for i in range(4))
+    return f"""(pcb socket (parser) (resolution um 10) (unit um)
+  (structure
+    (layer F.Cu (type signal)) (layer B.Cu (type signal))
+    (boundary (path pcb 0  125000 -115000  85000 -115000  85000 -75000  125000 -75000
+      125000 -115000))
+    (via "Via[0-1]_800:400_um")
+    (rule (width 300) (clearance 250)))
+  (placement
+    (component S (place P3 {cx} {cy} front {rotation}))
+    (component T {" ".join(places)}))
+  (library
+    (image S (pin R 1 0 0) (pin O 2 2540 0) (pin O 3 5080 0) (pin O 4 7620 0))
+    (image T (pin t 1 0 0))
+    (padstack O (shape (path F.Cu 1727.2 0 -152.4 0 152.4))
+      (shape (path B.Cu 1727.2 0 -152.4 0 152.4)) (attach off))
+    (padstack R (shape (rect F.Cu -863.6 -1016 863.6 1016))
+      (shape (rect B.Cu -863.6 -1016 863.6 1016)) (attach off))
+    (padstack t (shape (rect F.Cu -500 -500 500 500)) (attach off))
+    (padstack "Via[0-1]_800:400_um" (shape (circle F.Cu 800)) (shape (circle B.Cu 800))
+      (attach off)))
+  (network {nets}
+    (class c N0 N1 N2 N3 (circuit (use_via "Via[0-1]_800:400_um"))
+      (rule (width 300) (clearance 250)))))"""
+
+
+def test_a_rotated_oval_pad_is_its_outline_not_its_bounding_box():
+    board = build_board(parse_dsn(_socket_dsn(60, "y")))
+    oval = next(p for p in board.get_pins() if p.component_ref == "P3" and p.name == "2")
+    assert isinstance(oval.shape, Simplex) and not oval.shape.is_int_box()
+    box = oval.shape.bounding_box()
+    assert oval.shape.contains(oval.location)
+    assert not oval.shape.contains(box.ll) and not oval.shape.contains(box.ur)
+
+
+@pytest.mark.parametrize("layout", ["y", "perp"])
+def test_routes_leaving_a_rotated_socket_pass_the_exact_check(layout):
+    result = build_exact_routing_result(
+        parse_dsn(_socket_dsn(60, layout)), resolution=2, shove=True
+    )
+    assert result.unrouted == []
+
+
+# --- a via two connections share --------------------------------------------
+
+_SHARED_VIA = """(pcb shared (parser) (resolution um 10) (unit um)
+  (structure
+    (layer Top (type signal)) (layer Bottom (type signal))
+    (boundary (path pcb 0  0 0  20000 0  20000 -20000  0 -20000  0 0))
+    (via "Via[0-1]_800:400_um")
+    (rule (width 300) (clearance 250)))
+  (library
+    (padstack p (shape (rect Top -400 -400 400 400)) (attach off))
+    (padstack "Via[0-1]_800:400_um" (shape (circle Top 800)) (shape (circle Bottom 800))
+      (attach off))
+    (image PAD (pin p 1 0 0)))
+  (placement (component PAD
+    (place G1 3000 -5000 front 0) (place G2 3000 -15000 front 0)
+    (place G3 17000 -10000 front 0) (place S1 3000 -10000 front 0)
+    (place S2 17000 -3000 front 0)))
+  (network (net GND (pins G1-1 G2-1 G3-1)) (net SIG (pins S1-1 S2-1))))"""
+
+
+def _line(a, b, layer):
+    (x, y), (x1, y1) = a, b
+    out = [(x, y, layer)]
+    while x != x1:
+        x += 1 if x1 > x else -1
+        out.append((x, y, layer))
+    while y != y1:
+        y += 1 if y1 > y else -1
+        out.append((x, y, layer))
+    return out
+
+
+def test_a_shared_via_keeps_its_footprint_when_one_user_is_ripped():
+    dsn = parse_dsn(_SHARED_VIA)
+    s = dsn.resolution.value
+    router = GridRouter(
+        build_board(dsn),
+        trace_width=round(_rule_width_dsn(dsn) * s),
+        clearance=round(_rule_clearance_dsn(dsn) * s),
+        via_half=_via_half_board(dsn, s),
+    )
+    conns = router._conns = router._build_connections()
+    gnd = [c for c in conns if len({c.a.component_ref, c.b.component_ref} & {"G1", "G2", "G3"})]
+    sig = next(c for c in conns if c not in gnd)
+    first, second = gnd
+    g3 = router._cell_of(next(p for p in router.board.get_pins() if p.component_ref == "G3").location)
+    via = (g3[0] - 10, g3[1])
+
+    def through_via(conn):
+        a, b = router._cell_of(conn.a.location), router._cell_of(conn.b.location)
+        return _line(a, via, 0) + _line(via, b, 1)
+
+    router._commit(first, through_via(first))
+    router._commit(second, through_via(second))
+    footprint = [c for c in router._via_cells(via) if c != via]
+    router._rip(first)
+
+    assert second.routed and via in second.via_cells
+    assert all(router._via_claims.get(c) == [second.index] for c in footprint)
+    # another net still keeps its distance from the via that is left
+    assert all(router._enter_cost_base(c, 0, sig.net_no, False, conns) is None for c in footprint)
+
+
+def test_a_route_through_a_shared_via_rips_every_user():
+    """Two connections of a net share a via. Another net routed through it
+    in rip-up mode has to rip both, or the one left keeps its via under the
+    new trace and the exact check throws one of them out."""
+    dsn = parse_dsn(_SHARED_VIA)
+    s = dsn.resolution.value
+    router = GridRouter(
+        build_board(dsn),
+        trace_width=round(_rule_width_dsn(dsn) * s),
+        clearance=round(_rule_clearance_dsn(dsn) * s),
+        via_half=_via_half_board(dsn, s),
+    )
+    conns = router._conns = router._build_connections()
+    gnd = [c for c in conns if len({c.a.component_ref, c.b.component_ref} & {"G1", "G2", "G3"})]
+    sig = next(c for c in conns if c not in gnd)
+    first, second = gnd
+    g3 = router._cell_of(next(p for p in router.board.get_pins() if p.component_ref == "G3").location)
+    via = (g3[0] - 10, g3[1])
+
+    def through_via(conn):
+        a, b = router._cell_of(conn.a.location), router._cell_of(conn.b.location)
+        return _line(a, via, 0) + _line(via, b, 1)
+
+    router._commit(first, through_via(first))
+    router._commit(second, through_via(second))
+    # the via's copper alone: footprint cells no trace or trace halo covers
+    crossing = [
+        node
+        for c in router._via_cells(via)
+        for node in ((*c, 0), (*c, 1))
+        if node not in router._cell_owner and node not in router._halo
+    ]
+    assert crossing
+
+    assert router._crossed_owners(crossing, sig.net_no, conns) == {first.index, second.index}
+
+
+# --- a wider net class --------------------------------------------------------
+
+_WIDE = """(pcb wide (parser) (resolution um 10) (unit um)
+  (structure
+    (layer F.Cu (type signal))
+    (boundary (path pcb 0  0 0  20000 0  20000 -10000  0 -10000  0 0))
+    (rule (width 300) (clearance 250)))
+  (placement (component S (place P1 2000 -5000 front 0) (place P2 18000 -5000 front 0)
+     (place Q1 10000 {ylo} front 0) (place Q2 10000 {yhi} front 0)
+     (place Q3 10000 -1000 front 0) (place Q4 10000 -9000 front 0)))
+  (library (image S (pin pad 1 0 0)) (padstack pad (shape (rect F.Cu -600 -600 600 600)) (attach off)))
+  (network (net PWR (pins P1-1 P2-1)) (net SIG (pins Q1-1 Q3-1)) (net SIG2 (pins Q2-1 Q4-1))
+    (class Power PWR (rule (width 500) (clearance 250)))))"""
+
+
+@pytest.mark.parametrize("resolution", [1, 2])
+@pytest.mark.parametrize("gap", [900, 1000, 1075])
+def test_a_wide_net_past_pads_it_does_not_fit_between_is_not_refused(gap, resolution):
+    # 0.3 mm fits the gap between the two pads, 0.5 mm does not: the grid
+    # must see that, rather than lay it wide and have the exact check drop it
+    ylo, yhi = -5000 - gap // 2 - 600, -5000 + gap // 2 + 600
+    result = build_exact_routing_result(
+        parse_dsn(_WIDE.format(ylo=ylo, yhi=yhi)), resolution=resolution
+    )
+    assert result.unrouted == []
+
+
+def _wide_router():
+    dsn = parse_dsn(_WIDE.format(ylo=-6050, yhi=-3950))
+    s = dsn.resolution.value
+    pwr = next(i for i, net in enumerate(dsn.nets, 1) if net.name == "PWR")
+    return GridRouter(
+        build_board(dsn),
+        trace_width=round(_rule_width_dsn(dsn) * s),
+        clearance=round(_rule_clearance_dsn(dsn) * s),
+        resolution=2,
+        net_widths={pwr: 5000},
+    ), pwr
+
+
+def test_a_wide_trace_keeps_clear_of_a_default_one_at_the_grid_diagonal():
+    router, _pwr = _wide_router()
+    # 0.5 mm against 0.3 mm needs 0.25 + 0.25 + 0.15 = 0.65 mm between centres,
+    # on either axis, since the exact check compares boxes
+    need = 2500 + router.clearance + router.half_width
+    for dx, dy in [(2, 2), (2, 1), (1, 2)]:
+        assert max(dx, dy) * router.step < need
+        assert (dx, dy) in router._halo_for(2500)
+
+
+def test_a_wide_rip_up_route_counts_what_its_extra_width_crosses():
+    router, pwr_net = _wide_router()
+    conns = router._conns = router._build_connections()
+    pwr = next(c for c in conns if c.net_no == pwr_net)
+    other = next(c for c in conns if c.net_no != pwr_net)
+    # a default-width trace two cells from the wide route's path
+    x, y = 20, 5
+    router._commit(other, _line((x - 3, y + 2), (x + 3, y + 2), 0))
+    path = _line((x - 3, y), (x + 3, y), 0)
+    spread = router._spread_for(2500)
+    assert other.index not in router._crossed_owners(path, pwr.net_no, conns)
+    assert other.index in router._crossed_owners(path, pwr.net_no, conns, spread)
+
+
+def test_a_pad_cell_check_uses_the_rotated_outline():
+    board = build_board(parse_dsn(_socket_dsn(60, "y")))
+    router = GridRouter(board, trace_width=3000, clearance=2500, resolution=2)
+    oval = next(p for p in board.get_pins() if p.component_ref == "P3" and p.name == "2")
+    box = oval.shape.bounding_box()
+    margin = router.clearance + router.half_width
+    exact = set(router._pad_cells(oval.shape, box, margin))
+    boxed = set(router._cells_in_box(box, margin))
+    assert exact < boxed
+    for cell in boxed - exact:
+        c = router._cell_center(cell)
+        square = IntBox(c.x - margin, c.y - margin, c.x + margin, c.y + margin)
+        assert oval.shape.intersection(square).dimension() != 2
+
+
+def test_a_via_by_a_chamfered_corner_is_judged_round():
+    """The grid keeps a via's centre its radius plus the edge clearance from
+    the outline. The exact check used the via's square, whose corner reaches
+    past a 45-degree chamfer where the round via does not."""
+    from freeroute.board.outline import BoardOutline
+    from freeroute.geometry import IntBox, IntPoint
+    from freeroute.route.exact_router import _inside_outline
+
+    # a 10 mm square with its lower-left corner cut at 45 degrees
+    outline = BoardOutline([IntPoint(*p) for p in
+                            [(30, 0), (100, 0), (100, 100), (0, 100), (0, 30)]])
+    half, edge = 4, 1
+    via = IntPoint(19, 20)  # its centre 6.4 from the chamfer x + y = 30
+    square = IntBox(via.x - half, via.y - half, via.x + half, via.y + half)
+    assert not outline.box_clear(square, edge)  # the square's corner: 0.7 away
+    assert _inside_outline(outline, [], [via], half + edge, edge)
+    # 4.2 from the chamfer: the round via itself is too close
+    assert not _inside_outline(outline, [], [IntPoint(18, 18)], half + edge, edge)

tests/route/test_net_widths.py

@@ -0,0 +1,42 @@
+"""Net classes wider than the default are routed at their width where it fits."""
+
+from __future__ import annotations
+
+from freeroute.dsn import parse_dsn
+from freeroute.route.pipeline import build_exact_routing_result
+
+_BOARD = """(pcb widths (parser) (resolution um 10) (unit um)
+  (structure
+    (layer F.Cu (type signal))
+    (boundary (path pcb 0  0 0  20000 0  20000 -10000  0 -10000  0 0))
+    {keepouts}
+    (rule (width 150) (clearance 150)))
+  (placement (component S (place P1 2000 -5000 front 0) (place P2 18000 -5000 front 0)))
+  (library (image S (pin pad 1 0 0)) (padstack pad (shape (rect F.Cu -600 -600 600 600)) (attach off)))
+  (network (net PWR (pins P1-1 P2-1))
+    (class Power PWR (rule (width 400) (clearance 150)))))"""
+
+# two keepouts leave a 0.65 mm channel: room for 0.15 mm (0.45), not for 0.4 mm (0.7)
+_CHANNEL = (
+    '(keepout "" (polygon F.Cu 0  9000 0  11000 0  11000 -4675  9000 -4675))\n'
+    '    (keepout "" (polygon F.Cu 0  9000 -5325  11000 -5325  11000 -10000  9000 -10000))'
+)
+
+
+def _route(keepouts=""):
+    return build_exact_routing_result(parse_dsn(_BOARD.format(keepouts=keepouts)), resolution=2)
+
+
+def test_a_wider_class_is_routed_and_written_at_its_width():
+    result = _route()
+    assert result.unrouted == [] and result.narrowed == []
+    widths = {w.width for net in result.nets for w in net.wires}
+    assert widths == {400.0}
+
+
+def test_a_wider_class_that_does_not_fit_falls_back_to_the_default():
+    result = _route(_CHANNEL)
+    assert result.unrouted == []
+    assert [net for net, _a, _b in result.narrowed] == ["PWR"]
+    widths = {w.width for net in result.nets for w in net.wires}
+    assert widths == {150.0}

tests/route/test_real_board_geometry.py

@@ -51,19 +51,22 @@ def test_routes_keep_edge_clearance_at_a_rounded_corner():
                 assert outline.edge_distance(p) >= half + 500 * scale - 1
 
 
-@pytest.mark.parametrize(("resolution", "escape"), [(1, 2), (4, 5)])
-def test_every_pin_of_a_half_millimetre_pitch_row_escapes(resolution, escape):
+@pytest.mark.parametrize("resolution", [1, 4])
+def test_every_pin_of_a_half_millimetre_pitch_row_escapes(resolution):
     # Five 0.3 mm pads at 0.5 mm pitch, each wired to its own pad 8 mm away.
     # Between two neighbours a trace's centre has a legal band only 0.15 mm
-    # wide. At resolution 1 the 0.4 mm grid misses most bands; at 4 its
-    # 0.1 mm columns cannot, and every pin gets out, as the JAR manages.
+    # wide. At resolution 4 the 0.1 mm columns cannot miss it. At resolution
+    # 1 the 0.4 mm grid misses most bands, but a stub leaves its pin straight
+    # along the band and jogs to the column only past the pads, so every pin
+    # gets out there too, as the JAR manages (only 2 did before).
     places = " ".join(f"(place R{i} {6000 + 500 * i} -6000 front 0)" for i in range(5))
     places += " " + " ".join(f"(place F{i} {6000 + 500 * i} -14000 front 0)" for i in range(5))
     nets = " ".join(f"(net N{i} (pins R{i}-1 F{i}-1))" for i in range(5))
     result, _, _ = route_dsn_board_exact(
         parse_dsn(_dsn(f"(component P {places})", nets)), resolution=resolution
     )
-    assert len(result.routed_net_numbers) == escape
+    assert len(result.routed_net_numbers) == 5
+    assert result.drc_clean
 
 
 def test_resolution_one_has_no_halo_so_the_grid_is_unchanged():
@@ -223,3 +226,29 @@ def test_a_through_hole_pad_inside_a_plane_needs_no_route():
     groups = _connected_groups(gnd_pins, plane, frozenset(id(z) for z in plane))
     hub = next(g for g in groups if g[1])
     assert [p.component_ref for p in hub[0]] == ["GT"]
+
+
+def test_a_pad_inside_a_via_keepout_reaches_the_plane_by_a_via_outside_it():
+    # a sensor's GND pad: vias are forbidden under the body, so the route
+    # has to leave on the top layer and drop to the plane past the keepout
+    dsn = parse_dsn("""(pcb repro (parser) (resolution um 10) (unit um)
+  (structure
+    (layer F.Cu (type signal)) (layer In1.Cu (type power)) (layer In2.Cu (type power))
+    (layer B.Cu (type signal))
+    (boundary (path pcb 0  0 0  20000 0  20000 -20000  0 -20000  0 0))
+    (plane GND (polygon In1.Cu 0  500 -500  19500 -500  19500 -19500  500 -19500  500 -500))
+    (via_keepout "" (polygon signal 0  8500 -8500  11500 -8500  11500 -11500  8500 -11500  8500 -8500))
+    (via "Via[0-3]_600:300_um") (rule (width 150) (clearance 150)))
+  (placement (component S (place G1 10000 -10000 front 0)))
+  (library
+    (image S (pin smd 1 0 0))
+    (padstack smd (shape (rect F.Cu -175 -300 175 300)) (attach off))
+    (padstack "Via[0-3]_600:300_um" (shape (circle F.Cu 600)) (shape (circle B.Cu 600)) (attach off)))
+  (network (net GND (pins G1-1))))""")
+    exact, scale, _names = route_dsn_board_exact(dsn, resolution=2)
+    assert exact.result.failed == []
+    (via,) = exact.result.vias[1]
+    half = 300 * scale  # the via's radius
+    outside = (via.x + half <= 8500 * scale or via.x - half >= 11500 * scale
+               or via.y - half >= -8500 * scale or via.y + half <= -11500 * scale)
+    assert outside, f"via at {via} is inside the via keepout"

tests/route/test_rollback.py

@@ -31,7 +31,7 @@ def test_occupancy_only_holds_routed_connections(name):
     router, _ = _routed_router(name)
     conns = router._conns
     assert all(conns[i].routed for i in router._cell_owner.values())
-    assert all(conns[i].routed for i in router._via_owner.values())
+    assert all(conns[i].routed for claims in router._via_claims.values() for i in claims)
     assert all(conns[i].routed for claims in router._halo.values() for i in claims)
 
 

tests/route/test_straight_pin_exits.py

@@ -0,0 +1,58 @@
+"""Pins of a 1.27 mm pitch row routed at 1.0 mm (the RN2483 module on the
+TTN Enschede mote). A trace centre has to stay within 0.06 mm of a pin's
+centreline to pass its neighbours, which no grid column hits, so a route
+leaves each pin straight along that line and only jogs to its column once
+past the pads. FreeRouting routes this row in full the same way."""
+
+from __future__ import annotations
+
+import pytest
+
+from freeroute.board import build_board
+from freeroute.board.items import Pin
+from freeroute.dsn import parse_dsn
+from freeroute.geometry import IntPoint
+from freeroute.route.grid_router import GridRouter
+from freeroute.route.pipeline import route_dsn_board_exact
+
+
+def _row(x0: int, pins: int = 6, skew: int = 3000) -> str:
+    places = " ".join(f"(place R{i} {x0 + 1270 * i} -5000 front 0)" for i in range(pins))
+    places += " " + " ".join(
+        f"(place T{i} {x0 + 1270 * i + skew} -15000 front 0)" for i in range(pins)
+    )
+    nets = " ".join(f"(net N{i} (pins R{i}-1 T{i}-1))" for i in range(pins))
+    return f"""(pcb t (parser) (resolution um 10) (unit um)
+  (structure (layer F.Cu (type signal)) (layer B.Cu (type signal))
+    (boundary (path pcb 0 0 0 30000 0 30000 -20000 0 -20000 0 0))
+    (via "Via[0-1]_600:400_um") (rule (width 1000) (clearance 200)))
+  (placement (component P {places}))
+  (library (image P (pin pad 1 0 0))
+    (padstack pad (shape (rect F.Cu -508 -762 508 762)) (attach off))
+    (padstack "Via[0-1]_600:400_um" (shape (circle F.Cu 600)) (shape (circle B.Cu 600))
+      (attach off)))
+  (network {nets}))"""
+
+
+@pytest.mark.parametrize("x0", [5000, 5150, 5300])
+def test_every_pin_of_a_row_leaves_straight_and_routes(x0):
+    # three offsets of the row against the grid; before, 2 or 3 of 6 routed
+    result, _, _ = route_dsn_board_exact(parse_dsn(_row(x0)), resolution=2)
+    assert len(result.routed_net_numbers) == 6
+    assert result.drc_clean
+
+
+def test_a_walled_in_pin_may_escape_to_the_column_either_side():
+    # two pins side by side leaving the same way can then jog apart
+    board = build_board(parse_dsn(_row(5000)))
+    router = GridRouter(board, trace_width=10000, clearance=2000, orthogonal=True, resolution=2)
+    router._conns = router._build_connections()
+    pin = next(
+        p for p in board.get_items()
+        if isinstance(p, Pin) and p.location == IntPoint(50000 + 2 * 12700, -50000)
+    )
+    net = pin.net_nos[0]
+    cx, cy = router._cell_of(pin.location)
+    nodes = router._escape_nodes(pin, net, router._conns, [0], (cx, cy))
+    columns = {x for x, y, _ in nodes if y != cy}
+    assert {cx - 1, cx, cx + 1} <= columns

tests/route/test_via_spacing.py

@@ -0,0 +1,136 @@
+"""Vias keep hole-to-hole spacing, even within one net."""
+
+from __future__ import annotations
+
+import itertools
+import math
+
+from freeroute.dsn import parse_dsn
+from freeroute.route.pipeline import route_dsn_board_exact
+
+# four GND pads 0.5 mm apart over a GND plane: each drops a via to the plane
+_DSN = """(pcb holes (parser) (resolution um 10) (unit um)
+  (structure
+    (layer F.Cu (type signal)) (layer In1.Cu (type power)) (layer In2.Cu (type power))
+    (layer B.Cu (type signal))
+    (boundary (path pcb 0  0 0  20000 0  20000 -20000  0 -20000  0 0))
+    (plane GND (polygon In1.Cu 0  500 -500  19500 -500  19500 -19500  500 -19500  500 -500))
+    (via "Via[0-3]_500:300_um") (rule (width 150) (clearance 150)))
+  (placement (component S (place G1 9000 -10000 front 0) (place G2 9500 -10000 front 0)
+                          (place G3 10000 -10000 front 0) (place G4 10500 -10000 front 0)))
+  (library
+    (image S (pin smd 1 0 0))
+    (padstack smd (shape (rect F.Cu -150 -300 150 300)) (attach off))
+    (padstack "Via[0-3]_500:300_um" (shape (circle F.Cu 500)) (shape (circle B.Cu 500)) (attach off)))
+  (network (net GND (pins G1-1 G2-1 G3-1 G4-1))))"""
+
+
+def test_a_nets_own_vias_keep_hole_to_hole_spacing():
+    dsn = parse_dsn(_DSN)
+    exact, scale, _ = route_dsn_board_exact(dsn, resolution=2)
+    assert exact.result.failed == []
+    vias = exact.result.vias[1]
+    assert len(set(vias)) == len(vias), "a via written twice"
+    need = (300 + 250) * scale  # drill + 0.25 mm, centre to centre
+    for a, b in itertools.combinations(vias, 2):
+        assert math.hypot(a.x - b.x, a.y - b.y) >= need, f"vias at {a} and {b} too close"
+
+
+def test_connections_sharing_a_plane_via_write_it_once():
+    # eight GND pads 0.4 mm apart: the hole spacing makes several of them
+    # end on the same plane via, which must come out once, not once each
+    pads = " ".join(f"(place G{i} {9000 + 400 * i} -10000 front 0)" for i in range(8))
+    pins = " ".join(f"G{i}-1" for i in range(8))
+    dsn = parse_dsn(
+        _DSN.replace(
+            "(place G1 9000 -10000 front 0) (place G2 9500 -10000 front 0)\n"
+            "                          (place G3 10000 -10000 front 0) (place G4 10500 -10000 front 0)",
+            pads,
+        )
+        .replace("(pins G1-1 G2-1 G3-1 G4-1)", f"(pins {pins})")
+        .replace("(rect F.Cu -150 -300 150 300)", "(rect F.Cu -125 -300 125 300)")
+    )
+    exact, _scale, _ = route_dsn_board_exact(dsn, resolution=2)
+    vias = exact.result.vias[1]
+    assert len(vias) < 8, "no via is shared, so this board no longer tests sharing"
+    assert len(set(vias)) == len(vias), "a shared via written more than once"
+
+
+def _router(dsn_text, via_drill_um=300):
+    from freeroute.board import build_board
+    from freeroute.route.grid_router import GridRouter
+    from freeroute.route.pipeline import _rule_clearance_dsn, _rule_width_dsn
+
+    dsn = parse_dsn(dsn_text)
+    s = dsn.resolution.value
+    return GridRouter(
+        build_board(dsn), trace_width=round(_rule_width_dsn(dsn) * s),
+        clearance=round(_rule_clearance_dsn(dsn) * s), resolution=2, orthogonal=True,
+        via_drill=via_drill_um * s, hole_to_hole=250 * s,
+    ), s
+
+
+_THT = """(pcb tht (parser) (resolution um 10) (unit um)
+  (structure (layer F.Cu (type signal)) (layer B.Cu (type signal))
+    (boundary (path pcb 0  0 0  20000 0  20000 -20000  0 -20000  0 0))
+    (via "Via[0-1]_500:300_um") (rule (width 150) (clearance 150)))
+  (placement (component T (place J1 10000 -10000 front 0)))
+  (library (image T (pin tht 1 0 0))
+    (padstack tht (shape (circle F.Cu 1700)) (shape (circle B.Cu 1700)) (attach off))
+    (padstack "Via[0-1]_500:300_um" (shape (circle F.Cu 500)) (shape (circle B.Cu 500)) (attach off)))
+  (network (net SIG (pins J1-1))))"""
+
+
+def test_no_via_goes_near_a_through_hole_pads_hole_even_of_its_own_net():
+    router, s = _router(_THT)
+    pin = router._cell_of(router.board.get_pins()[0].location)
+    assert not router._holes_clear(pin, 1)  # own net, right on the pad
+    far = (pin[0] + 40, pin[1])
+    assert router._holes_clear(far, 1)
+
+
+def test_a_via_in_a_pad_keeps_hole_spacing_from_a_fixed_via():
+    from freeroute.geometry import IntPoint
+
+    text = _THT.replace("(network (net SIG (pins J1-1))))",
+                        "(network (net SIG (pins J1-1)))\n"
+                        "  (wiring (via \"Via[0-1]_500:300_um\"  3000 -3000 (net SIG) (type route))))")
+    router, s = _router(text)
+    assert not router._hole_clear_at(IntPoint(3400 * s, -3000 * s))  # 0.4 mm < 0.55 mm
+    assert router._hole_clear_at(IntPoint(3600 * s, -3000 * s))
+
+
+def test_hole_spacing_from_a_fixed_via_is_measured_from_where_it_really_is():
+    # a fixed via off the grid with its own 0.25 mm drill, and the router's
+    # via a smaller 0.2 mm one (the flight controller's case): a new via needs
+    # its centre 0.1 + 0.125 + 0.25 = 0.475 mm away, measured exactly, where
+    # one rule for all vias gave 0.2 + 0.25 = 0.45 from the cell centres
+    text = _THT.replace("(network (net SIG (pins J1-1))))",
+                        "(network (net SIG (pins J1-1)) (net GND))\n"
+                        "  (wiring (via \"Via[0-1]_500:250_um\"  3030 -3030 (net GND) (type route))))")
+    text = text.replace(
+        '(attach off)))\n  (network',
+        '(attach off))\n    (padstack "Via[0-1]_500:250_um" (shape (circle F.Cu 500)) '
+        '(shape (circle B.Cu 500)) (attach off)))\n  (network',
+    )
+    router, s = _router(text, via_drill_um=200)
+    via = next(v for v in router.board.get_items() if getattr(v, "drill", 0))
+    assert via.drill == 250 * s
+    loc = via.location
+    for cell in [(x, y) for x in range(router.cols) for y in range(router.rows)]:
+        c = router._cell_center(cell)
+        d = math.hypot(c.x - loc.x, c.y - loc.y)
+        if router.step * 1.5 < d < 470 * s:
+            assert not router._holes_clear(cell, 1), f"{d / s:.0f} um from the fixed via"
+        elif 560 * s < d < 700 * s and cell not in router._tht_block:
+            assert router._holes_clear(cell, 1)
+
+
+def test_a_route_keeps_its_own_vias_apart():
+    # a route that changed layer at (10, 10) may not change layer again one
+    # cell away; the same cell is the same through via, and far is fine
+    router, _s = _router(_THT)
+    came_from = {(10, 10, 1): (10, 10, 0), (11, 10, 1): (10, 10, 1), (12, 10, 1): (11, 10, 1)}
+    assert router._near_path_via((12, 10, 1), (11, 10), came_from)
+    assert not router._near_path_via((12, 10, 1), (10, 10), came_from)
+    assert not router._near_path_via((12, 10, 1), (40, 10), came_from)