Compare commits

...
Author SHA1 Message Date
rsp2k de9fb51bb3 --fanout: leave out pins a same-net pour on their layer already joins 2026-09-29 10:40:46 -06:00
rsp2k 74360f2f57 --fanout: only packages of --fanout-min-pins or more; supply-only mode; vias for signals that change layer 2026-09-29 10:20:11 -06:00
rsp2k 21c80d30f2 Tests: fan-out stubs go outward past their pads; a plane pin gets its via 2026-09-29 09:53:05 -06:00
rsp2k 2d686178af --fanout: commit a way out for every fine-pitch pin before routing (work in progress) 2026-09-29 09:52:35 -06:00
rsp2k 7a42230f36 Merge fix/fixed-via-holes: exact hole spacing to fixed vias, vias on one route kept apart 2026-09-29 09:13:47 -06:00
rsp2k 83ad0f8ef7 Keep a route's own vias apart while it is searched
Committed vias were checked for hole spacing, but a route's own vias are
not committed until it is done, so a route hopping layers (more of them
on 6 layers) could put two of its vias 0.41 mm apart, as th-eda's
6-layer flight controller showed. A via is now also checked against
layer changes earlier on its own route.
2026-09-29 03:10:52 -06:00
rsp2k 6e852a929b Hole spacing to a fixed via measured from where it is, with its own drill
A fixed via sits anywhere, not on a cell centre, and may have a bigger
drill than the router's via; checking hole spacing between cell centres
with one drill let the flight controller's routed 0.2 mm via come 0.19
mm from a hand-placed 0.25 mm one. The board now carries each fixed
via's drill (from KiCad's padstack name), and cells are checked against
fixed vias exactly.
2026-09-29 02:34:17 -06:00
rsp2k f56bb10996 Test: the session never repeats wiring already on the board 2026-09-29 01:17:59 -06:00
rsp2k 8f656006a6 Merge fix/hole-spacing-pads: hole spacing from through-hole pads and fixed vias 2026-09-29 01:16:59 -06:00
rsp2k 6cc2406583 Hole spacing also from through-hole pads and fixed vias
A route could drop a via next to (or onto) a through-hole pad of its own
net, where it changes layer for free, and a via reusing a fixed via's
cell came out a little off the fixed via's centre, beside it. No via now
goes within hole spacing of a through-hole pad of any net; a via in a pad
is checked exactly against every via and hole; and a routed via on a
fixed via of its net is not written. charge-sense: 4 hole_to_hole to 0;
flight controller: 2 to 0, unconnected unchanged.
2026-09-29 01:13:16 -06:00
rsp2k 30297e94dc Merge feat/net-widths: fixed wiring, plane via checks, class widths, via spacing, fan-out connectivity 2026-09-29 00:26:02 -06:00
rsp2k 45b3753cff Count copper already on the board as connections already made
Fixed tracks and vias only kept other nets away, so a pin fanned out to
its plane was routed to the plane again, beside its own fan-out. Pins,
zones and planes that fixed copper of their net touches now form one
connected group: a fanned-out supply pin needs nothing more, a fanned-out
signal routes from its via, and copper touching no pin or zone adds
nothing to route.
2026-09-29 00:16:56 -06:00
rsp2k 7d8e5d5c10 bench/diagnose.py: tell fixed copper, pads and keepouts apart as walls 2026-09-29 00:14:40 -06:00
rsp2k 8152619541 Write each plane via once in the exact engine's output too
The exact engine rebuilds its output from each connection's own vias,
so connections sharing a plane via each wrote a copy: th-eda's flight
controller had 71 spots carrying 2 to 4 vias of one net. Vias are now
written once per net and spot, and never on a via already on the board.
2026-09-28 23:56:23 -06:00
rsp2k 714fa873ae Keep hole-to-hole spacing between every two vias, one net's included
Every pin of a supply drops its own via to the plane, and nothing kept
two of them apart: the flight controller came back with 199 co-located
holes and 109 hole-to-hole errors, nearly all VDD_3V3 and GND. A via now
keeps its drill plus --hole-to-hole (default 0.25 mm, KiCad's) from
every via centre, fixed ones included, except an own-net via at the same
cell, which it reuses; such a via is written once, and none is written
on top of a via already on the board.
2026-09-28 21:52:52 -06:00
rsp2k 4a844e8cd7 Route wider net classes at their width, falling back where they don't fit
The grid is laid out for the default width; a wider trace also needs the
cells its extra half width reaches to be free, and claims a wider halo.
A connection that does not fit at its class width (typically at a
fine-pitch pin) is routed at the default instead and reported. A net is
written at its class width when all of its connections went in at it,
and the exact check verifies it at that width; nets that shove or the
diagonal pass reshaped go out at the default.
2026-09-28 21:16:40 -06:00
14 changed files with 1174 additions and 28 deletions
+32 -2
View File
@@ -106,6 +106,15 @@ def _capture_conflicts() -> list:
return log
def _wall_name(wall, names) -> str:
if isinstance(wall, str):
if wall.startswith("fixed copper of net "):
net = int(wall.rsplit(" ", 1)[1])
return f"fixed copper of {names.get(net, net)}"
return wall
return names.get(wall, "pads/keepouts")
def _gap(a, b) -> int:
dx = max(b.ll.x - a.ur.x, a.ll.x - b.ur.x, 0)
dy = max(b.ll.y - a.ur.y, a.ll.y - b.ur.y, 0)
@@ -118,6 +127,25 @@ def _fresh(seen) -> GridRouter:
return router
def _static_wall(router: GridRouter, node) -> str:
"""What static copper closes a node: a keepout, copper already on the
board (a fixed via or track, by net), or a pad."""
if node in router._keepout:
return "keepout"
fixed = getattr(router, "_diag_fixed", None)
if fixed is None:
fixed = router._diag_fixed = {}
margin = router.clearance + router.half_width
for net, layers, box in router.board.get_fixed_copper():
for cell in router._cells_in_box(box, margin):
for layer in layers:
fixed[(*cell, layer)] = net
net = fixed.get(node)
if net is not None:
return f"fixed copper of net {net}"
return "pads"
def _flood(router: GridRouter, pin, net_no: int, conns) -> tuple[int, Counter]:
"""How many nodes a pin can reach through free cells (up to FLOOD_LIMIT),
and which other nets' copper bounds the region."""
@@ -146,7 +174,7 @@ def _flood(router: GridRouter, pin, net_no: int, conns) -> tuple[int, Counter]:
for owner in owners:
walls[conns[owner].net_no] += 1
if not owners:
walls[0] += 1 # a pad or keepout
walls[_static_wall(router, n)] += 1
continue
seen.add(n)
frontier.append(n)
@@ -224,7 +252,9 @@ def diagnose(
if reach < FLOOD_LIMIT:
walled.append({
"pin": end, "reach": reach,
"walls": [names.get(n, "pads/keepouts") for n, _ in walls.most_common(4)],
"walls": [
_wall_name(n, names) for n, _ in walls.most_common(4)
],
})
row["kind"] = "walled-in" if walled else "congestion"
if walled:
+10 -1
View File
@@ -23,6 +23,7 @@ the containment invariant, and pads are centre-symmetric in practice).
from __future__ import annotations
import math
import re
from freeroute.dsn.model import DsnBoard
from freeroute.dsn.shapes import Circle, Path, Polygon, Rectangle, Shape
@@ -38,6 +39,9 @@ from .transform import CoordinateTransform
__all__ = ["build_board"]
# DSN units per micrometre, for drills KiCad gives in um in via padstack names
_DSN_PER_UM = {"um": 1.0, "mm": 0.001, "mil": 1 / 25.4, "inch": 1 / 25400}
def build_board(dsn: DsnBoard) -> BasicBoard:
"""Construct a :class:`BasicBoard` from a parsed :class:`DsnBoard`."""
@@ -503,10 +507,15 @@ def _insert_wiring(dsn: DsnBoard, board: BasicBoard, transform: CoordinateTransf
location = transform.dsn_to_board_point(via.x, via.y)
pad = _pad_tile(max(padstack.shapes, key=_shape_extent), transform)
box = pad.bounding_box()
drill = re.search(r"_([\d.]+):([\d.]+)_um", via.padstack)
drill_board = (
round(transform.dsn_to_board(float(drill.group(2)) * _DSN_PER_UM.get(dsn.unit, 1.0)))
if drill else 0
)
board.insert(
Via(
net_nos=[numbers[via.net]], fixed=True, padstack_name=via.padstack,
location=location, layers=sorted(layers or signal_layers),
drill=drill_board, location=location, layers=sorted(layers or signal_layers),
shape=IntBox(box.ll.x + location.x, box.ll.y + location.y,
box.ur.x + location.x, box.ur.y + location.y),
)
+6
View File
@@ -117,6 +117,10 @@ class Via(Item):
#: layer indices the via's pads occupy, and the largest pad as a box
layers: list[int] = field(default_factory=list)
shape: object = None
#: drill diameter in board units, when the padstack name gives it
drill: int = 0
#: placed by the router's fan-out, not on the board yet: written out
generated: bool = False
@dataclass
@@ -130,6 +134,8 @@ class Trace(Item):
layer: int = 0
half_width: int = 0
corners: list[IntPoint] = field(default_factory=list)
#: placed by the router's fan-out, not on the board yet: written out
generated: bool = False
def is_empty(self) -> bool:
return len(self.corners) < 2
+45 -2
View File
@@ -30,8 +30,11 @@ from freeroute.ses import write_ses
#: which optional flags each engine actually implements. Anything not listed for
#: an engine is rejected by :func:`_validate` rather than quietly ignored.
ENGINE_OPTIONS: dict[str, frozenset[str]] = {
"grid": frozenset({"rip_up", "max_passes", "seed", "orders", "promote", "access", "rollback"}),
"exact": frozenset({"shove", "diagonal", "rip_up", "max_passes", "seed", "orders", "promote", "access", "rollback"}),
"grid": frozenset({"rip_up", "max_passes", "seed", "orders", "promote", "access", "rollback", "fanout"}),
"exact": frozenset(
{"shove", "diagonal", "rip_up", "max_passes", "seed", "orders", "promote", "access",
"rollback", "fanout"}
),
"room": frozenset({"shove", "pack"}),
}
@@ -47,6 +50,7 @@ _FLAG_NAMES = {
"promote": "--promote-failures",
"access": "--access-cost",
"rollback": "--no-rollback",
"fanout": "--fanout",
}
@@ -175,6 +179,30 @@ def build_parser() -> argparse.ArgumentParser:
"connections a rip-up displaces are rerouted at once and the rip-up is undone "
"if fewer connections end up routed",
)
parser.add_argument(
"--hole-to-hole",
type=float,
default=0.25,
metavar="MM",
help="grid and exact engines: least distance between the edges of any two via "
"holes, of one net or two (KiCad's min_hole_to_hole; default 0.25)",
)
parser.add_argument(
"--fanout",
nargs="?",
const="all",
choices=["all", "supply"],
help="grid and exact engines: before routing, give every fine-pitch pin a stub "
"outward past its pad row (and a via to its plane, for a plane net), committed "
"as copper so later routes cannot wall it in; --fanout supply: plane pins only",
)
parser.add_argument(
"--fanout-min-pins",
type=int,
default=32,
metavar="N",
help="with --fanout: fan out only packages with at least N fine-pitch pins (default 32)",
)
parser.add_argument(
"--jobs",
type=int,
@@ -205,6 +233,7 @@ def main(argv: list[str] | None = None) -> int:
("promote", args.promote_failures is not None),
("access", args.access_cost is not None),
("rollback", not args.rollback),
("fanout", bool(args.fanout)),
)
if asked
]
@@ -239,6 +268,9 @@ def main(argv: list[str] | None = None) -> int:
"resolution": 2 if args.grid_resolution is None else args.grid_resolution,
"heuristic_weight": args.heuristic_weight,
"access_cost": args.access_cost or 0.0,
"hole_to_hole_mm": args.hole_to_hole,
"fanout": args.fanout or False,
"fanout_min_pins": args.fanout_min_pins,
"rollback": args.rollback,
}
elif args.engine == "grid":
@@ -249,6 +281,9 @@ def main(argv: list[str] | None = None) -> int:
"edge_clearance_mm": args.edge_clearance,
"resolution": 1 if args.grid_resolution is None else args.grid_resolution,
"access_cost": args.access_cost or 0.0,
"hole_to_hole_mm": args.hole_to_hole,
"fanout": args.fanout or False,
"fanout_min_pins": args.fanout_min_pins,
"rollback": args.rollback,
}
if args.engine == "room":
@@ -287,6 +322,14 @@ def main(argv: list[str] | None = None) -> int:
print(f"freeroute: {len(missing)} connection(s) not routed:", file=sys.stderr)
for net, a, b, _zone in missing:
print(f" {net}: {a} to {b}", file=sys.stderr)
if result.narrowed:
print(
f"freeroute: {len(result.narrowed)} connection(s) of a wider net class only fitted "
"at the default width; their nets are written at the default width:",
file=sys.stderr,
)
for net, a, b in result.narrowed:
print(f" {net}: {a} to {b}", file=sys.stderr)
if in_zone:
print(
f"freeroute: {len(in_zone)} more connection(s) left to a zone fill that may join them:",
+45 -5
View File
@@ -31,7 +31,7 @@ from dataclasses import dataclass, field
import math
from freeroute.board.board import BasicBoard
from freeroute.board.items import Pin
from freeroute.board.items import Pin, Via
from freeroute.board.search_tree import ShapeSearchTree, TreeShape
from freeroute.geometry import (
IntBox,
@@ -99,6 +99,9 @@ def route_board_exact(
route_first: frozenset | None = None,
access_cost: float = 0.0,
rollback: bool = True,
net_widths: dict[int, int] | None = None,
via_drill: int | None = None,
hole_to_hole: int = 0,
) -> ExactRouteResult:
"""Route ``board`` orthogonally and verify the result with exact geometry.
@@ -131,6 +134,9 @@ def route_board_exact(
route_first=route_first,
access_cost=access_cost,
rollback=rollback,
net_widths=net_widths,
via_drill=via_drill,
hole_to_hole=hole_to_hole,
)
edge = 0 if edge_clearance is None else edge_clearance
outline = board.outline
@@ -172,23 +178,32 @@ def route_board_exact(
via_layers = frozenset(signal_layers)
accepted: dict[int, _Accepted] = {}
fixed_vias = {
(item.net_nos[0], item.location)
for item in board.get_items()
if isinstance(item, Via) and item.fixed and item.net_nos
}
# Verify connection by connection, so one conflicting segment of a
# 25-pin supply net costs that one connection, not the whole net.
rejected: list[tuple[int, str, str]] = []
ends_list = result.connection_ends or [("?", "?", "")] * len(result.connections)
# each net is checked at the width it will be written at: its class's
# when all of its connections went in at that, else the default
net_half = dict(result.net_half)
for (net_no, wires, vias), ends in sorted(
zip(result.connections, ends_list, strict=False), key=lambda c: c[0][0]
):
boxes = _copper_boxes(wires, vias, half_width, via_layers, via_half)
wire_count = len(_copper_boxes(wires, [], half_width, via_layers, via_half))
wire_half = net_half.get(net_no, half_width)
boxes = _copper_boxes(wires, vias, wire_half, via_layers, via_half)
wire_count = len(_copper_boxes(wires, [], wire_half, via_layers, via_half))
if any(
tree.clearance_conflict(
box, net_no, layer, clearance, "wire" if i < wire_count else "via"
)
for i, (box, box_layers) in enumerate(boxes)
for layer in box_layers
) or _end_in_rule_area(tree, wires, half_width) or (
) or _end_in_rule_area(tree, wires, wire_half) or (
outline is not None and not all(outline.box_clear(b, edge) for b, _ in boxes)
):
rejected.append((net_no, *ends))
@@ -197,7 +212,12 @@ def route_board_exact(
if acc is None:
acc = accepted[net_no] = _Accepted(wires=[], vias=[])
acc.wires.extend(wires)
acc.vias.extend(vias)
# connections of one net that end on the same plane cell share its
# via: write it once, and never on top of a via already on the board
acc.vias.extend(
v for v in dict.fromkeys(vias)
if v not in acc.vias and not _on_fixed_via(net_no, v, fixed_vias, via_half)
)
for box, box_layers in boxes:
oid = next(owner)
tree.insert(TreeShape(oid, net_no, box_layers, box, routed=True))
@@ -247,6 +267,17 @@ def route_board_exact(
for net_no, acc in accepted.items():
clean.wires[net_no] = acc.wires
clean.vias[net_no] = acc.vias
# shove and the diagonal pass lay copper at the default width: nets they
# recovered, and nets whose traces shove pushed aside
reshaped = (set(accepted) - accepted_before_recovery) | {
net for net, acc in accepted.items() if acc.shove_count
}
if diagonal:
reshaped = set(accepted)
clean.net_half = {
net: half for net, half in net_half.items() if net in accepted and net not in reshaped
}
clean.narrowed = list(result.narrowed)
drc_clean = tree.has_violation(clearance) is None
return ExactRouteResult(result=clean, tree=tree, drc_clean=drc_clean, shoves=shoves)
@@ -615,6 +646,15 @@ def _end_in_rule_area(tree, wires, half_width) -> bool:
return False
def _on_fixed_via(net_no, point, fixed_vias, via_half) -> bool:
"""A routed via that reuses a via already on the board: the grid put it
on the fixed via's cell, a little off its centre, and it is not written."""
return any(
net == net_no and abs(loc.x - point.x) <= via_half and abs(loc.y - point.y) <= via_half
for net, loc in fixed_vias
)
def _copper_boxes(wires, vias, half_width, via_layers, via_half=None):
via_half = via_half or half_width
boxes: list[tuple[IntBox, frozenset[int]]] = []
+229
View File
@@ -0,0 +1,229 @@
"""Fan out fine-pitch pins before routing: commit each pin's way out as copper.
On a dense board the pins of a fine-pitch package get walled in: their own
neighbours' pads on either side, and other nets' copper that got there first
across the only way out. Reserving the way out did not help (the reserved
cells still had to be routed, and lost to congestion there); committing it
does, which is what a person does by hand.
Each fine-pitch pin of a perimeter package (QFP, QFN, LGA: pads on the edge,
none inside) gets a straight stub outward, perpendicular to its side of the
package, just past its pad row. A pin whose net has an inner plane also gets
a via at the stub's end, staggered between neighbouring pins so their holes
keep their spacing, and so reaches the plane with nothing left to route.
Every stub and via is checked exactly against pads, keepouts, the board edge,
copper already on the board and earlier fan-out, and left out where it would
not fit. The result goes on the board as fixed copper of its net (marked
``generated``), so the router starts from the stub's end or the via, and the
session writes it out with the routes.
"""
from __future__ import annotations
from dataclasses import dataclass
import math
from freeroute.board.board import BasicBoard
from freeroute.board.items import Pin, Trace, Via
from freeroute.geometry import IntBox, IntPoint
from freeroute.geometry.polyline import Polyline, PolylineShape, corner_box
# a package is fanned out when it has this many pins and they are this close
_MIN_PINS = 8
_FINE_PITCH_FACTOR = 1.2 # neighbour centres within this many (trace + 2 clearance)
@dataclass
class FanoutRules:
trace_width: int
clearance: int
via_half: int
via_drill: int
hole_to_hole: int
edge_clearance: int
signal_layers: list[int]
via_padstack: str
#: smallest package fanned out (a big dense part is where pins get walled in)
min_pins: int = 32
#: fan out plane pins only (a stub and a via each), as a person would first
supply_only: bool = False
def plan_fanout(board: BasicBoard, rules: FanoutRules) -> list:
"""The stubs and vias to put on the board before routing."""
half = max(rules.trace_width // 2, 1)
# a net may have several plane zones (a main plane and an island)
planes: dict[int, list] = {}
for z in board.get_conduction_areas():
if z.net_nos and not board.layer_structure.arr[z.layer].is_signal:
planes.setdefault(z.net_nos[0], []).append(z)
# copper pours on the routing layers, by net: a pad inside one is joined
# by the fill, and a stub there would take the room its thermal spokes need
pours: dict[int, list] = {}
for z in board.get_conduction_areas():
if z.net_nos and board.layer_structure.arr[z.layer].is_signal:
pours.setdefault(z.net_nos[0], []).append(z)
placed = _Placed(board, rules)
by_net: dict[int, list[Pin]] = {}
for pin in board.get_pins():
for n in pin.net_nos:
by_net.setdefault(n, []).append(pin)
items: list = []
pitch = 2 * rules.via_half + rules.hole_to_hole
for pins in _packages(board, rules).values():
centre = IntPoint(
sum(p.location.x for p in pins) // len(pins), sum(p.location.y for p in pins) // len(pins)
)
for k, pin in enumerate(sorted(pins, key=lambda p: (p.location.x, p.location.y))):
net = pin.net_nos[0] if pin.net_nos else None
if net is None:
continue
layer = next(layer for layer in pin.layers if layer in rules.signal_layers)
if any(z.layer == layer and z.polygon is not None and z.polygon.contains(pin.location)
for z in pours.get(net, [])):
continue # the pour joins it
direction = _outward(pin.location, centre)
reach = _pad_reach(pin, direction) + rules.clearance + half + rules.trace_width
end = _step(pin.location, direction, reach)
plane = planes.get(net)
partners = [q for q in by_net.get(net, []) if q is not pin]
# a signal whose other pins are all on other layers has to change
# layer somewhere: do it at the stub's end, away from the pads
elsewhere = bool(partners) and all(layer not in q.layers for q in partners)
if plane is None and (rules.supply_only or not elsewhere):
if not rules.supply_only and placed.stub_fits(pin.location, end, layer, net, half):
items.append(placed.add_stub(pin.location, end, layer, net, half))
continue
# stagger the via of every other pin along the side outward
options = [reach + rules.via_half + rules.clearance + (k % 2) * pitch,
reach + rules.via_half + rules.clearance + ((k + 1) % 2) * pitch]
for d in options:
at = _step(pin.location, direction, d)
if plane is not None and not any(
z.polygon is not None and z.polygon.contains(at) for z in plane
):
continue
if placed.stub_fits(pin.location, at, layer, net, half) and placed.via_fits(at, net):
items.append(placed.add_stub(pin.location, at, layer, net, half))
items.append(placed.add_via(at, net))
break
return items
def _packages(board: BasicBoard, rules: FanoutRules) -> dict[str, list[Pin]]:
"""Fine-pitch perimeter packages: many single-layer pins, close together."""
by_ref: dict[str, list[Pin]] = {}
for pin in board.get_pins():
if pin.shape is None or not pin.component_ref:
continue
on = [layer for layer in pin.layers if layer in rules.signal_layers]
if len(on) != 1:
continue # through-hole pins change layer for free
by_ref.setdefault(pin.component_ref, []).append(pin)
fine = _FINE_PITCH_FACTOR * (rules.trace_width + 2 * rules.clearance)
out = {}
for ref, pins in by_ref.items():
if len(pins) < max(rules.min_pins, _MIN_PINS):
continue
close = sum(
1 for p in pins
if min(math.hypot(p.location.x - q.location.x, p.location.y - q.location.y)
for q in pins if q is not p) < fine * 2
)
if close >= len(pins) // 2:
out[ref] = pins
return out
def _outward(point: IntPoint, centre: IntPoint) -> tuple[int, int]:
"""Away from the package centre, along the nearer axis (its side's normal)."""
dx, dy = point.x - centre.x, point.y - centre.y
if abs(dx) >= abs(dy):
return (1 if dx >= 0 else -1, 0)
return (0, 1 if dy >= 0 else -1)
def _pad_reach(pin: Pin, direction: tuple[int, int]) -> int:
"""How far the pad reaches from its centre in ``direction``."""
box = pin.shape.bounding_box()
if direction[0] > 0:
return box.ur.x - pin.location.x
if direction[0] < 0:
return pin.location.x - box.ll.x
if direction[1] > 0:
return box.ur.y - pin.location.y
return pin.location.y - box.ll.y
def _step(point: IntPoint, direction: tuple[int, int], distance: float) -> IntPoint:
return IntPoint(point.x + round(direction[0] * distance), point.y + round(direction[1] * distance))
class _Placed:
"""Copper a fan-out stub or via has to clear, growing as fan-out is placed."""
def __init__(self, board: BasicBoard, rules: FanoutRules) -> None:
self.board, self.rules = board, rules
self.copper: list[tuple[IntBox, frozenset[int], int]] = [] # box, layers, net
for pin in board.get_pins():
if pin.shape is not None:
net = pin.net_nos[0] if pin.net_nos else -1
self.copper.append((pin.shape.bounding_box(), frozenset(pin.layers), net))
for net, layers, box in board.get_fixed_copper():
self.copper.append((box, layers, net))
self.keepouts = [
(tile.bounding_box(), o.layer, o.blocks_wires, o.blocks_vias, o.clearance)
for o in board.get_obstacle_areas() for tile in o.tiles
]
self.holes: list[tuple[IntPoint, int]] = [] # centre, radius
for item in board.get_items():
if isinstance(item, Via) and item.fixed:
self.holes.append((item.location, (item.drill or rules.via_drill) // 2))
for pin in board.get_pins():
if pin.shape is not None and sum(1 for layer in pin.layers if layer in rules.signal_layers) > 1:
b = pin.shape.bounding_box()
self.holes.append((pin.location, min(b.ur.x - b.ll.x, b.ur.y - b.ll.y) // 2))
def _clear(self, box: IntBox, layers: frozenset[int], net: int, kind: str) -> bool:
grown = box.offset(self.rules.clearance)
for other, other_layers, other_net in self.copper:
if other_net != net and layers & other_layers and other.overlaps(grown):
return False
for kbox, klayer, wires, vias, needs in self.keepouts:
if klayer not in layers or not (wires if kind == "wire" else vias):
continue
if kbox.overlaps(grown if needs else box):
return False
outline = self.board.outline
return outline is None or outline.box_clear(box, self.rules.edge_clearance)
def stub_fits(self, a: IntPoint, b: IntPoint, layer: int, net: int, half: int) -> bool:
boxes = list(PolylineShape(Polyline([a, b]), half).tiles()) + [corner_box(b, half)]
return all(self._clear(box, frozenset({layer}), net, "wire") for box in boxes)
def via_fits(self, at: IntPoint, net: int) -> bool:
h = self.rules.via_half
box = IntBox(at.x - h, at.y - h, at.x + h, at.y + h)
if not self._clear(box, frozenset(self.rules.signal_layers), net, "via"):
return False
mine = self.rules.via_drill // 2
return all(
math.hypot(c.x - at.x, c.y - at.y) >= mine + r + self.rules.hole_to_hole
for c, r in self.holes
)
def add_stub(self, a: IntPoint, b: IntPoint, layer: int, net: int, half: int) -> Trace:
for box in list(PolylineShape(Polyline([a, b]), half).tiles()) + [corner_box(b, half)]:
self.copper.append((box, frozenset({layer}), net))
return Trace(net_nos=[net], fixed=True, layer=layer, half_width=half, corners=[a, b],
generated=True)
def add_via(self, at: IntPoint, net: int) -> Via:
h = self.rules.via_half
box = IntBox(at.x - h, at.y - h, at.x + h, at.y + h)
layers = list(self.rules.signal_layers)
self.copper.append((box, frozenset(layers), net))
self.holes.append((at, self.rules.via_drill // 2))
return Via(net_nos=[net], fixed=True, padstack_name=self.rules.via_padstack,
location=at, layers=layers, shape=box, drill=self.rules.via_drill,
generated=True)
+379 -17
View File
@@ -31,7 +31,7 @@ import math
import random
from freeroute.board.board import BasicBoard
from freeroute.board.items import ConductionArea, ObstacleArea, Pin
from freeroute.board.items import ConductionArea, ObstacleArea, Pin, Via
from freeroute.geometry import IntBox, IntPoint
from freeroute.geometry.polyline import corner_box
@@ -61,7 +61,10 @@ class RouteResult:
``routed_net_numbers`` are the nets that got any wire or via.
"""
__slots__ = ("wires", "vias", "half_width", "unrouted", "connections", "connection_ends", "failed")
__slots__ = (
"wires", "vias", "half_width", "unrouted", "connections", "connection_ends", "failed",
"net_half", "narrowed",
)
def __init__(self, half_width: int) -> None:
self.wires: dict[int, list[tuple[int, list[IntPoint]]]] = {}
@@ -76,6 +79,10 @@ class RouteResult:
self.connection_ends: list[tuple[str, str, str]] = []
#: connections left unrouted: (net_no, one end, the other end)
self.failed: list[tuple[int, str, str]] = []
#: half width of each net routed wider than the default (its class)
self.net_half: dict[int, int] = {}
#: connections of a wider class that only fitted at the default width
self.narrowed: list[tuple[int, str, str]] = []
def add_wire(self, net_no: int, layer: int, path: list[IntPoint]) -> None:
self.wires.setdefault(net_no, []).append((layer, path))
@@ -114,6 +121,8 @@ class _Connection:
"a_end",
"b_end",
"path",
"narrow",
"half",
)
def __init__(self, index: int, net_no: int, a: Pin, b: Pin) -> None:
@@ -137,6 +146,10 @@ class _Connection:
self.b_end: Pin | None = b
# the node path last committed, so a rip-up can be undone
self.path: list[Node] | None = None
# a connection of a wider class that did not fit at that width is
# routed at the default width instead; the half width it went in at
self.narrow = False
self.half = 0
class GridRouter:
@@ -163,6 +176,9 @@ class GridRouter:
route_first: frozenset | None = None,
access_cost: float = 0.0,
rollback: bool = True,
net_widths: dict[int, int] | None = None,
via_drill: int | None = None,
hole_to_hole: int = 0,
) -> None:
self.board = board
# Pin access: while a pin still has connections to route, the cells
@@ -223,6 +239,38 @@ class GridRouter:
self.edge_clearance = 0 if edge_clearance is None else edge_clearance
need = self.via_half + self.clearance + self.half_width
self.via_reach = max(0, math.ceil(need / self.step) - 1)
# Net classes wider than the default: the grid is laid out for the
# default width, so a wider trace must also find the cells around its
# own free, out to its extra half width, and claims a wider halo.
self._net_half = {
net: max(width // 2, 1)
for net, width in (net_widths or {}).items()
if width // 2 > self.half_width
}
self._spread: list[tuple[int, int]] = [] # the current search's
self._cur_half = self.half_width
self._halo_by_half: dict[int, list[tuple[int, int]]] = {self.half_width: self._halo_offsets}
# Hole-to-hole spacing holds between any two vias, of one net or two.
# Other nets' vias are kept further apart already; a net's own vias
# (every pin of a supply dropping to its plane) are not, so a via
# must keep its drill plus the spacing from every via centre, except
# an own-net via at the very same cell, which it simply reuses.
drill = via_drill if via_drill else 2 * self.via_half
need = drill + max(hole_to_hole, 0)
self._via_drill, self._hole_gap, self._hole_need = drill, max(hole_to_hole, 0), need
reach = math.ceil(need / self.step)
self._hole_offsets = [
(dx, dy)
for dx in range(-reach, reach + 1)
for dy in range(-reach, reach + 1)
if (dx or dy) and math.hypot(dx, dy) * self.step < need
]
self._via_nets: dict[Cell, dict[int, int]] = {} # routed via centres
self._via_centres: list[IntPoint] | None = None # cache for _hole_clear_at
self._fixed_vias: dict[Cell, int] = {}
# fixed vias sit anywhere, not on cell centres: exact hole checks
self._fixed_holes: list[tuple[IntPoint, int]] = []
self._fixed_via_points: set[tuple[int, IntPoint]] = set()
if layers is None:
layers = [i for i, layer in enumerate(board.layer_structure.arr) if layer.is_signal]
@@ -251,6 +299,28 @@ class GridRouter:
self._halo: dict[Node, list[int]] = {}
self._rasterize_obstacles()
self._rasterize_fixed_copper()
for item in board.get_items():
if isinstance(item, Via) and item.fixed and item.net_nos:
self._fixed_vias[self._cell_of(item.location)] = item.net_nos[0]
self._fixed_via_points.add((item.net_nos[0], item.location))
# its own drill, from KiCad's padstack name (Via[0-3]_500:250_um)
reach = self._via_drill // 2 + (item.drill or self._via_drill) // 2 + self._hole_gap
self._fixed_holes.append((item.location, reach))
# Through-hole pads have holes too, and a route changes layer at one
# for free, so no via (of any net) goes within hole spacing of one.
# The DSN has no drill for a pad; its smaller half size stands in.
self._tht_holes: list[tuple[IntPoint, int]] = []
self._tht_block: set[Cell] = set()
for pin in board.get_pins():
if pin.shape is None or sum(1 for layer in pin.layers if layer in self.layers) < 2:
continue
box = pin.shape.bounding_box()
radius = min(box.ur.x - box.ll.x, box.ur.y - box.ll.y) // 2
reach = radius + self._via_drill // 2 + self._hole_gap
self._tht_holes.append((pin.location, reach))
ring = IntBox(pin.location.x, pin.location.y, pin.location.x, pin.location.y)
for cell in self._cells_in_box(ring, reach):
self._tht_block.add(cell)
# --- grid helpers -------------------------------------------------------
@@ -386,6 +456,30 @@ class GridRouter:
allow_ripup: bool,
conns: list[_Connection],
wire_keepout: bool = True,
) -> float | None:
""":meth:`_enter_cost_base`, and for a trace wider than the default
the same for every cell its extra width reaches (the worst of them)."""
cost = self._enter_cost_base(cell, layer, net_no, allow_ripup, conns, wire_keepout)
if cost is None or not self._spread:
return cost
for dx, dy in self._spread:
c = (cell[0] + dx, cell[1] + dy)
if not (0 <= c[0] < self.cols and 0 <= c[1] < self.rows):
return None
more = self._enter_cost_base(c, layer, net_no, allow_ripup, conns, wire_keepout)
if more is None:
return None
cost = max(cost, more)
return cost
def _enter_cost_base(
self,
cell: Cell,
layer: int,
net_no: int,
allow_ripup: bool,
conns: list[_Connection],
wire_keepout: bool = True,
) -> float | None:
"""Cost to enter ``(cell, layer)`` for ``net_no``; ``None`` if blocked.
@@ -440,14 +534,101 @@ class GridRouter:
for layer in self.layers:
if (*c, layer) in self._via_keepout:
return False
if self._enter_cost(c, layer, net_no, False, conns, wire_keepout=False) != 0.0:
if self._enter_cost_base(c, layer, net_no, False, conns, wire_keepout=False) != 0.0:
return False
return True
return self._holes_clear(cell, net_no)
def _near_path_via(self, node: Node, cell: Cell, came_from: dict) -> bool:
"""A layer change earlier on the route that reaches ``node`` sits
within hole spacing of ``cell`` (and is not the same through via).
Committed vias are checked elsewhere; a route's own are not yet
committed while it is searched. Looks back far enough to cover the
hole spacing twice over, not along the whole route."""
limit = 4 * (math.ceil(self._hole_need / self.step) + 1)
need = self._hole_need / self.step
steps = 0
while node in came_from and steps < limit:
prev = came_from[node]
changes_layer = prev[:2] == node[:2] and prev[2] != node[2]
if changes_layer and node[:2] != cell and (
math.hypot(node[0] - cell[0], node[1] - cell[1]) < need
):
return True
node = prev
steps += 1
return False
def _via_nets_at(self, cell: Cell) -> set[int]:
nets = {net for net, n in self._via_nets.get(cell, {}).items() if n > 0}
fixed = self._fixed_vias.get(cell)
if fixed is not None:
nets.add(fixed)
return nets
def _holes_clear(self, cell: Cell, net_no: int) -> bool:
"""No via centre within hole-to-hole reach, but an own-net one here,
and no through-hole pad's hole within reach at all."""
if cell in self._tht_block:
return False
if self._fixed_holes:
here = self._cell_center(cell)
for loc, reach in self._fixed_holes:
d = math.hypot(loc.x - here.x, loc.y - here.y)
if d < reach and d > self.step: # beyond its own cell: too close
return False
if self._via_nets_at(cell) - {net_no}:
return False
cx, cy = cell
return not any(self._via_nets_at((cx + dx, cy + dy)) for dx, dy in self._hole_offsets)
# --- A* search ----------------------------------------------------------
def _conn_half(self, conn: _Connection) -> int:
"""The half width a connection is routed at: its class's, unless it
has fallen back to the default."""
return self.half_width if conn.narrow else self._net_half.get(conn.net_no, self.half_width)
def _spread_for(self, half: int) -> list[tuple[int, int]]:
"""Cells a trace of ``half`` also needs free: those whose centre is
within its extra half width (plus half a cell, for the grid)."""
extra = half - self.half_width
if extra <= 0:
return []
reach = math.ceil(extra / self.step) + 1
limit = extra + self.step / 2
return [
(dx, dy)
for dx in range(-reach, reach + 1)
for dy in range(-reach, reach + 1)
if (dx or dy) and math.hypot(dx, dy) * self.step <= limit
]
def _halo_for(self, half: int) -> list[tuple[int, int]]:
"""Cells a committed trace of ``half`` claims from default-width traces."""
offsets = self._halo_by_half.get(half)
if offsets is None:
need = half + self.clearance + self.half_width
reach = math.ceil(need / self.step)
offsets = self._halo_by_half[half] = [
(dx, dy)
for dx in range(-reach, reach + 1)
for dy in range(-reach, reach + 1)
if (dx or dy) and math.hypot(dx, dy) * self.step < need
]
return offsets
def _search(
self, conn: _Connection, allow_ripup: bool, conns: list[_Connection]
) -> list[Node] | None:
half = self._conn_half(conn)
self._cur_half, self._spread = half, self._spread_for(half)
try:
return self._search_at_width(conn, allow_ripup, conns)
finally:
self._cur_half, self._spread = self.half_width, []
def _search_at_width(
self, conn: _Connection, allow_ripup: bool, conns: list[_Connection]
) -> list[Node] | None:
goal_cell = self._group_target(conn.b_group)
if not conn.b_group[0] and any(z.layer in self._power_layers for z in conn.b_group[1]):
@@ -503,6 +684,8 @@ class GridRouter:
pin = ends.get(node)
if ok and isinstance(pin, Pin) and self._walled(node):
ok = self._via_fits_at(pin.location, net_no)
if ok and self._near_path_via(source, cell, came_from):
ok = False # too close to a via earlier on this same route
if ok:
self._relax(source, target, g_via, goal_cell, g_score, came_from, open_heap)
continue
@@ -514,6 +697,8 @@ class GridRouter:
ok = via_ok.get(cell)
if ok is None:
ok = via_ok[cell] = self._via_placeable(cell, net_no, conns)
if ok and self._near_path_via(current, cell, came_from):
ok = False
else:
ok = True
if ok:
@@ -587,14 +772,30 @@ class GridRouter:
]
copper += [(box, net) for net, _, box in self.board.get_fixed_copper()]
self._static_copper = copper
return not any(net != net_no and box.overlaps(grown) for box, net in self._static_copper)
if any(net != net_no and box.overlaps(grown) for box, net in self._static_copper):
return False
return self._hole_clear_at(point)
def _stub_cells(self, pin_location: IntPoint, cell: Cell) -> list[Cell]:
def _hole_clear_at(self, point: IntPoint) -> bool:
"""Hole spacing measured exactly from ``point`` to every via and
through-hole pad (a via moved into a pad is not on its cell's centre)."""
need = self._hole_need
if self._via_centres is None: # rebuilt only after vias change
self._via_centres = [loc for _net, loc in self._fixed_via_points] + [
self._cell_center(c) for c, count in self._via_nets.items() if any(count.values())
]
if any(math.hypot(c.x - point.x, c.y - point.y) < need for c in self._via_centres):
return False
return not any(
math.hypot(loc.x - point.x, loc.y - point.y) < reach for loc, reach in self._tht_holes
)
def _stub_cells(self, pin_location: IntPoint, cell: Cell, half: int | None = None) -> list[Cell]:
"""Cells where another net's trace would come too close to the stub."""
from freeroute.board.outline import _point_segment
end = self._cell_center(cell)
reach = 2 * self.half_width + self.clearance
reach = (half or self._cur_half) + self.half_width + self.clearance
box = IntBox(
min(pin_location.x, end.x), min(pin_location.y, end.y),
max(pin_location.x, end.x), max(pin_location.y, end.y),
@@ -616,12 +817,12 @@ class GridRouter:
end = self._cell_center(cell)
if end != pin.location:
for tile in PolylineShape(Polyline([pin.location, end]), self.half_width).tiles():
for tile in PolylineShape(Polyline([pin.location, end]), self._cur_half).tiles():
grown = tile.offset(self.clearance)
if any(k.overlaps(grown if needs else tile) for k, needs in keepouts):
return False
# the track's round end at the pin, for a rule area
cap = corner_box(pin.location, self.half_width)
cap = corner_box(pin.location, self._cur_half)
if any(not needs and k.overlaps(cap) for k, needs in keepouts):
return False
if keepouts_only:
@@ -860,11 +1061,18 @@ class GridRouter:
via_cells.append((path[-1][0], path[-1][1]))
conn.trace_cells = [(cell, layer) for layer, cells in wire_segs for cell in cells]
conn.via_cells = list(via_cells)
for cell in conn.via_cells:
count = self._via_nets.setdefault(cell, {})
count[conn.net_no] = count.get(conn.net_no, 0) + 1
if conn.via_cells:
self._via_centres = None
for cell, layer in conn.trace_cells:
self._cell_owner[(*cell, layer)] = conn.index
conn.half = half = self._conn_half(conn)
halo = self._halo_for(half)
conn.halo_nodes = []
for (cx, cy), layer in conn.trace_cells:
for dx, dy in self._halo_offsets:
for dx, dy in halo:
x, y = cx + dx, cy + dy
if 0 <= x < self.cols and 0 <= y < self.rows:
node = (x, y, layer)
@@ -881,7 +1089,7 @@ class GridRouter:
if not isinstance(pin, Pin):
continue # ended on a zone or a plane: no stub
cell = cells[at]
for c in self._stub_cells(pin.location, cell):
for c in self._stub_cells(pin.location, cell, half):
node = (*c, layer)
if node not in self._cell_owner:
self._cell_owner[node] = conn.index
@@ -932,6 +1140,12 @@ class GridRouter:
del self._halo[node]
conn.halo_nodes = []
conn.trace_cells = []
for cell in conn.via_cells:
count = self._via_nets.get(cell)
if count and count.get(conn.net_no):
count[conn.net_no] -= 1
if conn.via_cells:
self._via_centres = None
conn.via_cells = []
conn.wires = []
conn.vias = []
@@ -1012,6 +1226,7 @@ class GridRouter:
best_count = -1
best_snapshot: list[tuple[int, list, list]] | None = None
best_unrouted = len(conns)
best_widths: tuple[dict[int, int], list] = ({}, [])
# conns[i].index == i is what rip-up relies on, so shuffle a view
order = list(conns)
if self.seed is not None:
@@ -1031,13 +1246,25 @@ class GridRouter:
best_count = routed_count
best_unrouted = len(conns) - routed_count
best_snapshot = self._snapshot(conns)
best_widths = self._net_widths(conns)
if routed_count == len(conns):
break
if not changed:
break
return self._result_from(best_snapshot or [], best_unrouted)
result = self._result_from(best_snapshot or [], best_unrouted)
result.net_half, result.narrowed = best_widths
return result
def _try_route(self, conn: _Connection, conns: list[_Connection]) -> bool:
if self._route_once(conn, conns):
return True
if conn.narrow or conn.net_no not in self._net_half:
return False
# a wider class that does not fit: route it at the default width
conn.narrow = True
return self._route_once(conn, conns)
def _route_once(self, conn: _Connection, conns: list[_Connection]) -> bool:
path = self._search(conn, allow_ripup=False, conns=conns)
if path is None:
if not self.rip_up:
@@ -1101,7 +1328,9 @@ class GridRouter:
# deterministic: fewer-pin nets first, then by net number
for net_no in sorted(nets, key=lambda n: (len(pins_by_net.get(n, [])), n)):
zones = zones_by_net.get(net_no, []) + planes_by_net.get(net_no, [])
groups = _connected_groups(pins_by_net.get(net_no, []), zones, plane_ids)
groups = _connected_groups(
pins_by_net.get(net_no, []), zones, plane_ids, self._fixed_pieces(net_no)
)
hubs = [g for g in groups if any(id(z) in plane_ids for z in g[1])]
if hubs:
# a plane net: every other group goes straight to the plane
@@ -1115,6 +1344,28 @@ class GridRouter:
conns.append(conn)
return conns
def _fixed_pieces(self, net_no: int) -> list[_FixedPiece]:
"""The net's tracks and vias already on the board, as connectivity."""
cache = getattr(self, "_fixed_cache", None)
if cache is None:
from freeroute.board.items import Trace
from freeroute.geometry.polyline import Polyline, PolylineShape, corner_box
cache = self._fixed_cache = {}
for item in self.board.get_items():
if not item.fixed or not item.net_nos:
continue
if isinstance(item, Via) and item.shape is not None:
piece = _FixedPiece(item.layers, [item.shape.bounding_box()], via=item)
elif isinstance(item, Trace) and not item.is_empty():
boxes = list(PolylineShape(Polyline(item.corners), item.half_width).tiles())
boxes += [corner_box(e, item.half_width) for e in (item.corners[0], item.corners[-1])]
piece = _FixedPiece([item.layer], boxes, trace=item)
else:
continue
cache.setdefault(item.net_nos[0], []).append(piece)
return cache.get(net_no, [])
def _pins_by_net(self) -> dict[int, list[Pin]]:
by_net: dict[int, list[Pin]] = {}
for pin in self.board.get_pins():
@@ -1124,6 +1375,21 @@ class GridRouter:
by_net.setdefault(net_no, []).append(pin)
return by_net
def _net_widths(self, conns: list[_Connection]) -> tuple[dict[int, int], list]:
"""Half width of each wider-class net whose routed connections all went
in at it (a net is written at one width), and the connections that
had to fall back to the default."""
halves: dict[int, int] = {}
narrowed = []
for c in conns:
if not c.routed:
continue
halves[c.net_no] = min(halves.get(c.net_no, c.half), c.half)
if c.narrow:
narrowed.append((c.net_no, *_ends_of(c)))
wide = {net: half for net, half in halves.items() if half > self.half_width}
return wide, narrowed
def _snapshot(self, conns: list[_Connection]) -> list[tuple]:
return [
(c.net_no, [(layer, list(pts)) for layer, pts in c.wires], list(c.vias),
@@ -1134,11 +1400,16 @@ class GridRouter:
def _result_from(self, snapshot, unrouted: int) -> RouteResult:
result = RouteResult(self.half_width)
written: set[tuple[int, IntPoint]] = set()
result.unrouted = unrouted
for net_no, wires, vias, ends in snapshot:
for layer, points in wires:
result.add_wire(net_no, layer, points)
for location in vias:
spot = (net_no, location)
if spot in written or spot in self._fixed_via_points:
continue # a via reused by another connection, or already on the board
written.add(spot)
result.add_via(net_no, location)
result.connections.append((net_no, wires, vias))
result.connection_ends.append(ends)
@@ -1189,13 +1460,50 @@ def _pin_touches_zone(pin: Pin, zone, plane: bool = False) -> bool:
return any(zone.polygon.contains(c) for c in corners)
def _touches(a: IntBox, b: IntBox) -> bool:
return not (a.ur.x < b.ll.x or b.ur.x < a.ll.x or a.ur.y < b.ll.y or b.ur.y < a.ll.y)
def _fixed_joins_zone(piece, zone, plane: bool) -> bool:
"""A through via inside a plane joins it; copper inside a zone on its
own layer joins that zone."""
if zone.polygon is None:
return False
if piece.via is not None:
if plane or zone.layer in piece.layers:
return zone.polygon.contains(piece.via.location)
return False
return zone.layer in piece.layers and any(
zone.polygon.contains(IntPoint((b.ll.x + b.ur.x) // 2, (b.ll.y + b.ur.y) // 2))
for b in piece.boxes
)
class _FixedPiece:
"""One track or via already on the board, as connectivity."""
__slots__ = ("layers", "boxes", "via", "trace")
def __init__(self, layers, boxes, via=None, trace=None) -> None:
self.layers = frozenset(layers)
self.boxes = boxes
self.via = via # the Via item, for a via
self.trace = trace # the Trace item, for a track
def _connected_groups(
pins: list[Pin], zones: list, planes: frozenset = frozenset()
pins: list[Pin], zones: list, planes: frozenset = frozenset(), fixed: list | None = None
) -> list[tuple[list[Pin], list]]:
"""Pins and zones of one net that copper already joins: a pad in a zone
is connected to it, and two zones sharing a pad are one. Only the groups
need routing between them. Pin groups come first, in pin order."""
parent = list(range(len(pins) + len(zones)))
is connected to it, two zones sharing a pad are one, and copper already
on the board (tracks and vias, ``fixed``) joins whatever it touches. Only
the groups need routing between them. Pin groups come first, in pin
order. A group's fixed vias join its pins as extra route ends, so a
fanned-out pin is routed from its via; copper that touches no pin and no
zone adds nothing to route."""
fixed = fixed or []
n_pins, n_zones = len(pins), len(zones)
parent = list(range(n_pins + n_zones + len(fixed)))
def find(i: int) -> int:
while parent[i] != i:
@@ -1207,6 +1515,24 @@ def _connected_groups(
for i, pin in enumerate(pins):
if _pin_touches_zone(pin, zone, id(zone) in planes):
parent[find(i)] = find(len(pins) + j)
base = n_pins + n_zones
for k, piece in enumerate(fixed):
me = base + k
for i, pin in enumerate(pins):
if pin.shape is None or not piece.layers & set(pin.layers):
continue
pad = pin.shape.bounding_box()
if any(_touches(pad, b) for b in piece.boxes):
parent[find(i)] = find(me)
for j, zone in enumerate(zones):
if _fixed_joins_zone(piece, zone, id(zone) in planes):
parent[find(n_pins + j)] = find(me)
for k2 in range(k):
other = fixed[k2]
if piece.layers & other.layers and any(
_touches(a, b) for a in piece.boxes for b in other.boxes
):
parent[find(base + k2)] = find(me)
groups: dict[int, tuple[list[Pin], list]] = {}
order: list[int] = []
for i, pin in enumerate(pins):
@@ -1221,9 +1547,39 @@ def _connected_groups(
groups[root] = ([], [])
order.append(root)
groups[root][1].append(zone)
for k, piece in enumerate(fixed):
root = find(base + k)
if root not in groups:
continue
if piece.via is not None:
groups[root][0].append(_via_end(piece.via))
elif piece.trace is not None:
# a track's ends are places a route may start: a fan-out stub's
# far end is outside the pad row the pin sat walled in by
for end in (piece.trace.corners[0], piece.trace.corners[-1]):
groups[root][0].append(_trace_end(piece.trace, end))
return [groups[r] for r in order]
def _trace_end(trace, end: IntPoint) -> Pin:
"""An end of a fixed track as a place a route may start or end."""
from freeroute.geometry.polyline import corner_box
return Pin(
net_nos=list(trace.net_nos), fixed=True, name="track", component_ref="",
location=end, layers=[trace.layer], shape=corner_box(end, trace.half_width),
)
def _via_end(via) -> Pin:
"""A fixed via as a place a route may start or end (not a pad to route)."""
return Pin(
net_nos=list(via.net_nos), fixed=True, name="via", component_ref="",
padstack_name=via.padstack_name, location=via.location,
layers=list(via.layers), shape=via.shape,
)
def _split_path(path: list[Node]) -> tuple[list[tuple[int, list[Cell]]], list[Cell]]:
"""Split a node path into per-layer wire segments and via cells."""
wires: list[tuple[int, list[Cell]]] = []
@@ -1284,6 +1640,9 @@ def route_board(
route_first: frozenset | None = None,
access_cost: float = 0.0,
rollback: bool = True,
net_widths: dict[int, int] | None = None,
via_drill: int | None = None,
hole_to_hole: int = 0,
) -> RouteResult:
"""Convenience wrapper: build a :class:`GridRouter` and route the board."""
router = GridRouter(
@@ -1303,5 +1662,8 @@ def route_board(
route_first=route_first,
access_cost=access_cost,
rollback=rollback,
net_widths=net_widths,
via_drill=via_drill,
hole_to_hole=hole_to_hole,
)
return router.route()
+110 -1
View File
@@ -12,6 +12,8 @@ to DSN units (dividing by the resolution) for the SES ``(wire (path ...))`` and
from __future__ import annotations
import re
from freeroute.board import build_board
from freeroute.dsn import DsnBoard, parse_dsn
from freeroute.ses import RoutedVia, RoutedWire, RoutingResult, write_ses
@@ -34,6 +36,25 @@ def _rule_width_dsn(dsn: DsnBoard) -> float:
return rules[0].value if rules else _DEFAULT_WIDTH_DSN
def _net_widths_board(dsn: DsnBoard, scale: int) -> dict[int, int]:
"""Track width of every net whose class asks for more than the default,
in board units, by net number (build_board numbers nets in DSN order)."""
default = _rule_width_dsn(dsn)
by_name: dict[str, float] = {}
for net_class in dsn.net_classes:
if not net_class.width_rules:
continue
width = net_class.width_rules[0].value
if width > default:
for name in net_class.net_names:
by_name[name] = max(by_name.get(name, 0.0), width)
return {
i + 1: round(by_name[net.name] * scale)
for i, net in enumerate(dsn.nets)
if net.name in by_name
}
def _rule_clearance_dsn(dsn: DsnBoard) -> float:
for rule in dsn.structure_rules.clearance_rules:
if not rule.class_pairs: # the layer-wide default clearance
@@ -53,6 +74,56 @@ def _mm_to_board(dsn: DsnBoard, scale: int, value_mm: float | None) -> int | Non
return round(value_mm / unit_mm * scale)
def _via_drill_board(dsn: DsnBoard, scale: int) -> int | None:
"""The via's drill in board units, from KiCad's padstack name
(``Via[0-1]_600:300_um`` is a 600 um pad with a 300 um drill); None when
the name does not say, and the pad size stands in for it."""
match = re.search(r"_([\d.]+):([\d.]+)_um", _via_padstack(dsn))
if not match:
return None
return round(float(match.group(2)) * _dsn_units_per_um(dsn) * scale)
def _dsn_units_per_um(dsn: DsnBoard) -> float:
return {"um": 1.0, "mm": 0.001, "mil": 1 / 25.4, "inch": 1 / 25400}.get(dsn.unit, 1.0)
def _place_fanout(
board, dsn, scale, layers, width, clearance, edge, hole_to_hole_mm, mode=True, min_pins=32
) -> None:
"""Put the fan-out's stubs and vias on the board, before routing."""
from .fanout import FanoutRules, plan_fanout
via_half = _via_half_board(dsn, scale) or max(width // 2, 1)
rules = FanoutRules(
trace_width=width,
clearance=clearance,
via_half=via_half,
via_drill=_via_drill_board(dsn, scale) or 2 * via_half,
hole_to_hole=_mm_to_board(dsn, scale, hole_to_hole_mm) or 0,
edge_clearance=edge or 0,
signal_layers=layers or [i for i, layer in enumerate(dsn.layers) if layer.is_signal],
via_padstack=_via_padstack(dsn),
min_pins=min_pins,
supply_only=mode == "supply",
)
for item in plan_fanout(board, rules):
board.insert(item)
def _add_generated(result, board) -> None:
"""The fan-out's copper goes into the session with the routes."""
from freeroute.board.items import Trace, Via
for item in board.get_items():
if not getattr(item, "generated", False) or not item.net_nos:
continue
if isinstance(item, Trace):
result.add_wire(item.net_nos[0], item.layer, list(item.corners))
elif isinstance(item, Via):
result.add_via(item.net_nos[0], item.location)
def _via_half_board(dsn: DsnBoard, scale: int) -> int | None:
"""Half the via pad's size in board units, from the DSN's via padstack.
@@ -83,6 +154,9 @@ def route_dsn_board(
seed: int | None = None,
route_first: frozenset | None = None,
access_cost: float = 0.0,
hole_to_hole_mm: float = 0.25,
fanout: bool | str = False,
fanout_min_pins: int = 32,
rollback: bool = True,
) -> tuple[RouteResult, int, list[str]]:
"""Route a parsed :class:`DsnBoard`; return the board-unit result, the scale,
@@ -94,6 +168,9 @@ def route_dsn_board(
edge_clearance_board = _mm_to_board(dsn, scale, edge_clearance_mm)
width_board = round(_rule_width_dsn(dsn) * scale)
clearance_board = round(_rule_clearance_dsn(dsn) * scale)
if fanout:
_place_fanout(board, dsn, scale, layers, width_board, clearance_board,
edge_clearance_board, hole_to_hole_mm, fanout, fanout_min_pins)
result = route_board(
board,
resolution=resolution,
@@ -108,7 +185,11 @@ def route_dsn_board(
route_first=route_first,
access_cost=access_cost,
rollback=rollback,
net_widths=_net_widths_board(dsn, scale),
via_drill=_via_drill_board(dsn, scale),
hole_to_hole=_mm_to_board(dsn, scale, hole_to_hole_mm) or 0,
)
_add_generated(result, board)
return result, scale, [layer.name for layer in dsn.layers]
@@ -122,6 +203,9 @@ def _to_routing_result(route, dsn: DsnBoard, scale: int, layer_names: list[str])
result = RoutingResult()
for net_no, segments in route.wires.items():
name = numbers_to_names.get(net_no, str(net_no))
# its class's width when every connection of the net went in at it
half = getattr(route, "net_half", {}).get(net_no)
net_width = 2 * half / scale if half else width_dsn
for layer_index, path in segments:
layer_name = layer_names[layer_index] if layer_index < len(layer_names) else "F.Cu"
coords: list[float] = []
@@ -129,7 +213,7 @@ def _to_routing_result(route, dsn: DsnBoard, scale: int, layer_names: list[str])
coords.append(point.x / scale)
coords.append(point.y / scale)
if len(coords) >= 4:
result.add_wire(name, RoutedWire(layer=layer_name, width=width_dsn, coords=coords))
result.add_wire(name, RoutedWire(layer=layer_name, width=net_width, coords=coords))
for net_no, locations in route.vias.items():
name = numbers_to_names.get(net_no, str(net_no))
for loc in locations:
@@ -137,6 +221,9 @@ def _to_routing_result(route, dsn: DsnBoard, scale: int, layer_names: list[str])
result.unrouted = [
(numbers_to_names.get(n, str(n)), a, b, zone) for n, a, b, zone in getattr(route, "failed", [])
]
result.narrowed = [
(numbers_to_names.get(n, str(n)), a, b) for n, a, b in getattr(route, "narrowed", [])
]
return result
@@ -151,6 +238,9 @@ def build_routing_result(
seed: int | None = None,
route_first: frozenset | None = None,
access_cost: float = 0.0,
hole_to_hole_mm: float = 0.25,
fanout: bool | str = False,
fanout_min_pins: int = 32,
rollback: bool = True,
) -> RoutingResult:
"""Route ``dsn`` (grid track) and convert to a DSN-unit RoutingResult."""
@@ -159,6 +249,9 @@ def build_routing_result(
edge_clearance_mm=edge_clearance_mm, resolution=resolution, seed=seed,
route_first=route_first,
access_cost=access_cost,
hole_to_hole_mm=hole_to_hole_mm,
fanout=fanout,
fanout_min_pins=fanout_min_pins,
rollback=rollback,
)
return _to_routing_result(route, dsn, scale, layer_names)
@@ -178,6 +271,9 @@ def route_dsn_board_exact(
seed: int | None = None,
route_first: frozenset | None = None,
access_cost: float = 0.0,
hole_to_hole_mm: float = 0.25,
fanout: bool | str = False,
fanout_min_pins: int = 32,
rollback: bool = True,
) -> tuple[ExactRouteResult, int, list[str]]:
"""Route a parsed :class:`DsnBoard` with the exact-geometry (orthogonal,
@@ -190,6 +286,9 @@ def route_dsn_board_exact(
edge_clearance_board = _mm_to_board(dsn, scale, edge_clearance_mm)
width_board = round(_rule_width_dsn(dsn) * scale)
clearance_board = round(_rule_clearance_dsn(dsn) * scale)
if fanout:
_place_fanout(board, dsn, scale, layers, width_board, clearance_board,
edge_clearance_board, hole_to_hole_mm, fanout, fanout_min_pins)
exact = route_board_exact(
board,
resolution=resolution,
@@ -207,7 +306,11 @@ def route_dsn_board_exact(
route_first=route_first,
access_cost=access_cost,
rollback=rollback,
net_widths=_net_widths_board(dsn, scale),
via_drill=_via_drill_board(dsn, scale),
hole_to_hole=_mm_to_board(dsn, scale, hole_to_hole_mm) or 0,
)
_add_generated(exact.result, board)
return exact, scale, [layer.name for layer in dsn.layers]
@@ -225,6 +328,9 @@ def build_exact_routing_result(
seed: int | None = None,
route_first: frozenset | None = None,
access_cost: float = 0.0,
hole_to_hole_mm: float = 0.25,
fanout: bool | str = False,
fanout_min_pins: int = 32,
rollback: bool = True,
) -> RoutingResult:
"""Route ``dsn`` (exact track) and convert to a DSN-unit RoutingResult."""
@@ -241,6 +347,9 @@ def build_exact_routing_result(
seed=seed,
route_first=route_first,
access_cost=access_cost,
hole_to_hole_mm=hole_to_hole_mm,
fanout=fanout,
fanout_min_pins=fanout_min_pins,
rollback=rollback,
)
return _to_routing_result(exact.result, dsn, scale, layer_names)
+3
View File
@@ -60,6 +60,9 @@ class RoutingResult:
#: connections the router could not make: (net name, one end, other end,
#: the zone both ends sit in or "") -- a zone's fill may join the latter
unrouted: list[tuple[str, str, str, str]] = field(default_factory=list)
#: connections of a wider net class that only fitted at the default width
#: (net name, one end, other end); their net is written at the default
narrowed: list[tuple[str, str, str]] = field(default_factory=list)
def net(self, name: str, *, create: bool = False) -> RoutedNet | None:
"""Return the :class:`RoutedNet` with ``name`` (creating it if asked)."""
+78
View File
@@ -0,0 +1,78 @@
"""--fanout: fine-pitch pins get their way out committed before routing."""
from __future__ import annotations
from freeroute.board import build_board
from freeroute.board.items import Trace, Via
from freeroute.dsn import parse_dsn
from freeroute.route.fanout import FanoutRules, plan_fanout
from freeroute.route.pipeline import route_dsn_board_exact
# a 12-pad package, 3 pads a side at 0.5 mm pitch, over a GND plane on In1;
# pad 1 (left side, top) is GND, the rest are signals to far connector pads
_SIDES = {
"L": [(-2000, y, 0) for y in (500, 0, -500)],
"R": [(2000, y, 0) for y in (500, 0, -500)],
"T": [(x, 2000, 90) for x in (-500, 0, 500)],
"B": [(x, -2000, 90) for x in (-500, 0, 500)],
}
_PADS = [p for side in "LRTB" for p in _SIDES[side]]
def _dsn():
pins = "\n ".join(
f"(pin {'padv' if r else 'padh'} {i + 1} {x} {y})" for i, (x, y, r) in enumerate(_PADS)
)
far = " ".join(f"(place C{i} {3000 + 2000 * (i % 5)} {-12000 - 2000 * (i // 5)} front 0)" for i in range(11))
nets = "(net GND (pins U1-1))\n " + "\n ".join(f"(net S{i} (pins U1-{i + 2} C{i}-1))" for i in range(11))
return f"""(pcb pkg (parser) (resolution um 10) (unit um)
(structure
(layer F.Cu (type signal)) (layer In1.Cu (type power)) (layer In2.Cu (type power))
(layer B.Cu (type signal))
(boundary (path pcb 0 -15000 15000 25000 15000 25000 -25000 -15000 -25000 -15000 15000))
(plane GND (polygon In1.Cu 0 -14500 14500 24500 14500 24500 -24500 -14500 -24500 -14500 14500))
(via "Via[0-3]_450:200_um") (rule (width 150) (clearance 150)))
(placement (component Q (place U1 0 0 front 0)) (component P {far}))
(library
(image Q
{pins})
(image P (pin padc 1 0 0))
(padstack padh (shape (rect F.Cu -400 -125 400 125)) (attach off))
(padstack padv (shape (rect F.Cu -125 -400 125 400)) (attach off))
(padstack padc (shape (rect F.Cu -500 -500 500 500)) (attach off))
(padstack "Via[0-3]_450:200_um" (shape (circle F.Cu 450)) (shape (circle B.Cu 450)) (attach off)))
(network {nets}))"""
def _rules(dsn):
s = dsn.resolution.value
return FanoutRules(trace_width=150 * s, clearance=150 * s, via_half=225 * s, via_drill=200 * s,
hole_to_hole=250 * s, edge_clearance=0, signal_layers=[0, 3],
via_padstack="Via[0-3]_450:200_um", min_pins=8)
def test_every_pin_gets_a_stub_outward_past_its_pad():
dsn = parse_dsn(_dsn())
board = build_board(dsn)
items = plan_fanout(board, _rules(dsn))
stubs = [i for i in items if isinstance(i, Trace)]
assert len(stubs) == 12
for stub in stubs:
a, b = stub.corners
pin = next(p for p in board.get_pins() if p.location == a)
pad = pin.shape.bounding_box()
# outward: the stub ends further from the package centre, outside its pad
assert abs(b.x) + abs(b.y) > abs(a.x) + abs(a.y)
assert not (pad.ll.x <= b.x <= pad.ur.x and pad.ll.y <= b.y <= pad.ur.y)
def test_a_plane_pin_gets_a_via_and_needs_no_route():
dsn = parse_dsn(_dsn())
board = build_board(dsn)
items = plan_fanout(board, _rules(dsn))
assert len([i for i in items if isinstance(i, Via)]) == 1
exact, _scale, _ = route_dsn_board_exact(dsn, resolution=2, fanout=True, fanout_min_pins=8)
gnd = next(i + 1 for i, n in enumerate(dsn.nets) if n.name == "GND")
assert not any(f[0] == gnd for f in exact.result.failed)
assert exact.drc_clean
assert len(exact.result.vias.get(gnd, [])) == 1 # the fan-out's, written out
+58
View File
@@ -48,3 +48,61 @@ def test_other_nets_route_around_a_fixed_track():
continue
for p, q in zip(pts, pts[1:], strict=False):
assert not (min(p.x, q.x) < wall < max(p.x, q.x)), "crossed the GND track on F.Cu"
# --- fixed wiring as connectivity ------------------------------------------
_FANOUT = """(pcb fanout (parser) (resolution um 10) (unit um)
(structure
(layer F.Cu (type signal)) (layer In1.Cu (type power)) (layer In2.Cu (type power))
(layer B.Cu (type signal))
(boundary (path pcb 0 0 0 30000 0 30000 -20000 0 -20000 0 0))
(plane GND (polygon In1.Cu 0 500 -500 29500 -500 29500 -19500 500 -19500 500 -500))
(via "Via[0-3]_600:300_um") (rule (width 150) (clearance 150)))
(placement (component S (place G1 5000 -10000 front 0) (place A 10000 -10000 front 0)
(place B 25000 -11500 back 0)))
(library
(image S (pin smd 1 0 0))
(padstack smd (shape (rect F.Cu -300 -300 300 300)) (attach off))
(padstack "Via[0-3]_600:300_um" (shape (circle F.Cu 600)) (shape (circle B.Cu 600)) (attach off)))
(network (net GND (pins G1-1)) (net SIG (pins A-1 B-1)))
(wiring
(wire (path F.Cu 150 5000 -10000 5000 -11500) (net GND) (type route))
(via "Via[0-3]_600:300_um" 5000 -11500 (net GND) (type route))
(wire (path F.Cu 150 10000 -10000 10000 -11500) (net SIG) (type route))
(via "Via[0-3]_600:300_um" 10000 -11500 (net SIG) (type route))
(wire (path F.Cu 300 2000 -2000 8000 -2000) (net GND) (type route))))"""
def test_a_pad_fanned_out_to_its_plane_needs_no_route():
dsn = parse_dsn(_FANOUT)
exact, _scale, _names = route_dsn_board_exact(dsn, resolution=2)
gnd = next(i + 1 for i, n in enumerate(dsn.nets) if n.name == "GND")
assert exact.result.failed == []
assert not exact.result.vias.get(gnd) and not exact.result.wires.get(gnd)
def test_a_fanned_out_signal_is_routed_from_its_via():
# B is on the bottom face, level with A's fan-out via: starting from that
# via on B.Cu is the cheapest way, and needs no via of its own
dsn = parse_dsn(_FANOUT)
exact, scale, names = route_dsn_board_exact(dsn, resolution=2)
sig = next(i + 1 for i, n in enumerate(dsn.nets) if n.name == "SIG")
assert sig in exact.result.routed_net_numbers
assert not exact.result.vias.get(sig), "the fan-out via is already there"
assert {names[layer] for layer, _ in exact.result.wires[sig]} == {"B.Cu"}
def test_the_session_never_repeats_copper_already_on_the_board():
# the JAR writes the DSN's wiring back into its session, and an applier
# then adds it a second time on top of itself; freeroute writes only
# what it routed
from freeroute.route.pipeline import build_exact_routing_result
fixed_vias = {(5000.0, -11500.0), (10000.0, -11500.0)}
fixed_paths = {(5000.0, -10000.0, 5000.0, -11500.0), (10000.0, -10000.0, 10000.0, -11500.0),
(2000.0, -2000.0, 8000.0, -2000.0)}
result = build_exact_routing_result(parse_dsn(_FANOUT), resolution=2)
for net in result.nets:
assert not {(v.x, v.y) for v in net.vias} & fixed_vias
assert not {tuple(w.coords) for w in net.wires} & fixed_paths
+42
View File
@@ -0,0 +1,42 @@
"""Net classes wider than the default are routed at their width where it fits."""
from __future__ import annotations
from freeroute.dsn import parse_dsn
from freeroute.route.pipeline import build_exact_routing_result
_BOARD = """(pcb widths (parser) (resolution um 10) (unit um)
(structure
(layer F.Cu (type signal))
(boundary (path pcb 0 0 0 20000 0 20000 -10000 0 -10000 0 0))
{keepouts}
(rule (width 150) (clearance 150)))
(placement (component S (place P1 2000 -5000 front 0) (place P2 18000 -5000 front 0)))
(library (image S (pin pad 1 0 0)) (padstack pad (shape (rect F.Cu -600 -600 600 600)) (attach off)))
(network (net PWR (pins P1-1 P2-1))
(class Power PWR (rule (width 400) (clearance 150)))))"""
# two keepouts leave a 0.65 mm channel: room for 0.15 mm (0.45), not for 0.4 mm (0.7)
_CHANNEL = (
'(keepout "" (polygon F.Cu 0 9000 0 11000 0 11000 -4675 9000 -4675))\n'
' (keepout "" (polygon F.Cu 0 9000 -5325 11000 -5325 11000 -10000 9000 -10000))'
)
def _route(keepouts=""):
return build_exact_routing_result(parse_dsn(_BOARD.format(keepouts=keepouts)), resolution=2)
def test_a_wider_class_is_routed_and_written_at_its_width():
result = _route()
assert result.unrouted == [] and result.narrowed == []
widths = {w.width for net in result.nets for w in net.wires}
assert widths == {400.0}
def test_a_wider_class_that_does_not_fit_falls_back_to_the_default():
result = _route(_CHANNEL)
assert result.unrouted == []
assert [net for net, _a, _b in result.narrowed] == ["PWR"]
widths = {w.width for net in result.nets for w in net.wires}
assert widths == {150.0}
+136
View File
@@ -0,0 +1,136 @@
"""Vias keep hole-to-hole spacing, even within one net."""
from __future__ import annotations
import itertools
import math
from freeroute.dsn import parse_dsn
from freeroute.route.pipeline import route_dsn_board_exact
# four GND pads 0.5 mm apart over a GND plane: each drops a via to the plane
_DSN = """(pcb holes (parser) (resolution um 10) (unit um)
(structure
(layer F.Cu (type signal)) (layer In1.Cu (type power)) (layer In2.Cu (type power))
(layer B.Cu (type signal))
(boundary (path pcb 0 0 0 20000 0 20000 -20000 0 -20000 0 0))
(plane GND (polygon In1.Cu 0 500 -500 19500 -500 19500 -19500 500 -19500 500 -500))
(via "Via[0-3]_500:300_um") (rule (width 150) (clearance 150)))
(placement (component S (place G1 9000 -10000 front 0) (place G2 9500 -10000 front 0)
(place G3 10000 -10000 front 0) (place G4 10500 -10000 front 0)))
(library
(image S (pin smd 1 0 0))
(padstack smd (shape (rect F.Cu -150 -300 150 300)) (attach off))
(padstack "Via[0-3]_500:300_um" (shape (circle F.Cu 500)) (shape (circle B.Cu 500)) (attach off)))
(network (net GND (pins G1-1 G2-1 G3-1 G4-1))))"""
def test_a_nets_own_vias_keep_hole_to_hole_spacing():
dsn = parse_dsn(_DSN)
exact, scale, _ = route_dsn_board_exact(dsn, resolution=2)
assert exact.result.failed == []
vias = exact.result.vias[1]
assert len(set(vias)) == len(vias), "a via written twice"
need = (300 + 250) * scale # drill + 0.25 mm, centre to centre
for a, b in itertools.combinations(vias, 2):
assert math.hypot(a.x - b.x, a.y - b.y) >= need, f"vias at {a} and {b} too close"
def test_connections_sharing_a_plane_via_write_it_once():
# eight GND pads 0.4 mm apart: the hole spacing makes several of them
# end on the same plane via, which must come out once, not once each
pads = " ".join(f"(place G{i} {9000 + 400 * i} -10000 front 0)" for i in range(8))
pins = " ".join(f"G{i}-1" for i in range(8))
dsn = parse_dsn(
_DSN.replace(
"(place G1 9000 -10000 front 0) (place G2 9500 -10000 front 0)\n"
" (place G3 10000 -10000 front 0) (place G4 10500 -10000 front 0)",
pads,
)
.replace("(pins G1-1 G2-1 G3-1 G4-1)", f"(pins {pins})")
.replace("(rect F.Cu -150 -300 150 300)", "(rect F.Cu -125 -300 125 300)")
)
exact, _scale, _ = route_dsn_board_exact(dsn, resolution=2)
vias = exact.result.vias[1]
assert len(vias) < 8, "no via is shared, so this board no longer tests sharing"
assert len(set(vias)) == len(vias), "a shared via written more than once"
def _router(dsn_text, via_drill_um=300):
from freeroute.board import build_board
from freeroute.route.grid_router import GridRouter
from freeroute.route.pipeline import _rule_clearance_dsn, _rule_width_dsn
dsn = parse_dsn(dsn_text)
s = dsn.resolution.value
return GridRouter(
build_board(dsn), trace_width=round(_rule_width_dsn(dsn) * s),
clearance=round(_rule_clearance_dsn(dsn) * s), resolution=2, orthogonal=True,
via_drill=via_drill_um * s, hole_to_hole=250 * s,
), s
_THT = """(pcb tht (parser) (resolution um 10) (unit um)
(structure (layer F.Cu (type signal)) (layer B.Cu (type signal))
(boundary (path pcb 0 0 0 20000 0 20000 -20000 0 -20000 0 0))
(via "Via[0-1]_500:300_um") (rule (width 150) (clearance 150)))
(placement (component T (place J1 10000 -10000 front 0)))
(library (image T (pin tht 1 0 0))
(padstack tht (shape (circle F.Cu 1700)) (shape (circle B.Cu 1700)) (attach off))
(padstack "Via[0-1]_500:300_um" (shape (circle F.Cu 500)) (shape (circle B.Cu 500)) (attach off)))
(network (net SIG (pins J1-1))))"""
def test_no_via_goes_near_a_through_hole_pads_hole_even_of_its_own_net():
router, s = _router(_THT)
pin = router._cell_of(router.board.get_pins()[0].location)
assert not router._holes_clear(pin, 1) # own net, right on the pad
far = (pin[0] + 40, pin[1])
assert router._holes_clear(far, 1)
def test_a_via_in_a_pad_keeps_hole_spacing_from_a_fixed_via():
from freeroute.geometry import IntPoint
text = _THT.replace("(network (net SIG (pins J1-1))))",
"(network (net SIG (pins J1-1)))\n"
" (wiring (via \"Via[0-1]_500:300_um\" 3000 -3000 (net SIG) (type route))))")
router, s = _router(text)
assert not router._hole_clear_at(IntPoint(3400 * s, -3000 * s)) # 0.4 mm < 0.55 mm
assert router._hole_clear_at(IntPoint(3600 * s, -3000 * s))
def test_hole_spacing_from_a_fixed_via_is_measured_from_where_it_really_is():
# a fixed via off the grid with its own 0.25 mm drill, and the router's
# via a smaller 0.2 mm one (the flight controller's case): a new via needs
# its centre 0.1 + 0.125 + 0.25 = 0.475 mm away, measured exactly, where
# one rule for all vias gave 0.2 + 0.25 = 0.45 from the cell centres
text = _THT.replace("(network (net SIG (pins J1-1))))",
"(network (net SIG (pins J1-1)) (net GND))\n"
" (wiring (via \"Via[0-1]_500:250_um\" 3030 -3030 (net GND) (type route))))")
text = text.replace(
'(attach off)))\n (network',
'(attach off))\n (padstack "Via[0-1]_500:250_um" (shape (circle F.Cu 500)) '
'(shape (circle B.Cu 500)) (attach off)))\n (network',
)
router, s = _router(text, via_drill_um=200)
via = next(v for v in router.board.get_items() if getattr(v, "drill", 0))
assert via.drill == 250 * s
loc = via.location
for cell in [(x, y) for x in range(router.cols) for y in range(router.rows)]:
c = router._cell_center(cell)
d = math.hypot(c.x - loc.x, c.y - loc.y)
if router.step * 1.5 < d < 470 * s:
assert not router._holes_clear(cell, 1), f"{d / s:.0f} um from the fixed via"
elif 560 * s < d < 700 * s and cell not in router._tht_block:
assert router._holes_clear(cell, 1)
def test_a_route_keeps_its_own_vias_apart():
# a route that changed layer at (10, 10) may not change layer again one
# cell away; the same cell is the same through via, and far is fine
router, _s = _router(_THT)
came_from = {(10, 10, 1): (10, 10, 0), (11, 10, 1): (10, 10, 1), (12, 10, 1): (11, 10, 1)}
assert router._near_path_via((12, 10, 1), (11, 10), came_from)
assert not router._near_path_via((12, 10, 1), (10, 10), came_from)
assert not router._near_path_via((12, 10, 1), (40, 10), came_from)
+1
View File
@@ -159,6 +159,7 @@ def test_cli_supported_combinations_are_accepted(tmp_path):
"promote": ["--promote-failures", "2"],
"access": ["--access-cost", "5"],
"rollback": ["--no-rollback"],
"fanout": ["--fanout"],
}
for engine, options in ENGINE_OPTIONS.items():
for option in options: